CEONOS NVM Cell Using ONO Stack for Low-Voltage Programming
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Solution Overview
Problem
Current many-times programmable (MTP) non-volatile memory (NVM) cells for CMOS integrated circuits require complex manufacturing processes, large deviations from standard CMOS process flows, or result in large cell sizes, making them costly and inefficient in terms of size and endurance.
Innovation Solution
The development of a Cost-Efficient SONOS (CEONOS) NVM cell that uses a standard CMOS process flow with minimal modifications, featuring a polysilicon gate over an Oxide-Nitride-Oxide (ONO) stack structure for high-density, low-voltage programming and erasing, and enhanced lateral field engineering for hot electron programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing MTP NVM cell structures are used, then non-volatile memory functionality is achieved, but the cell size becomes too large and manufacturing complexity increases
Solution Approach 1:
The patent applies universality by making the ONO stack structure serve multiple functions: it acts as both the gate dielectric layer and contains the nitride trapping region for non-volatile memory operation. This eliminates the need for separate floating gate structures, thereby reducing cell size while maintaining MTP NVM functionality.
Solution Approach 2:
The patent implements nesting by placing the nitride layer within the ONO stack structure, where the nitride trapping region is embedded between the lower oxide and upper oxide layers. This nested configuration allows the memory function to be integrated within the standard transistor gate structure, minimizing additional area requirements.
2Reliability
If existing MTP NVM cell structures are used, then non-volatile memory functionality is achieved, but the manufacturing process complexity increases with additional masks and process steps
Solution Approach 1:
The ONO stack structure serves dual purposes as both the gate dielectric and the memory storage medium, eliminating the need for separate floating gate formation processes. This reduces manufacturing complexity while maintaining full MTP NVM functionality.
Solution Approach 2:
The patent modifies the gate dielectric parameters by using an ONO stack with specific thickness ranges (lower oxide: 50-200Å, nitride: 50-150Å, upper oxide: 50-200Å) that enable both standard transistor operation and non-volatile memory function, thereby simplifying the overall manufacturing process.
3Ease of manufacture
If standard CMOS process flow is used, then manufacturing cost is minimized, but non-volatile memory components cannot be produced
Solution Approach 1:
The patent modifies standard CMOS parameters by introducing the ONO stack with specific thickness parameters that enable NVM functionality. These parameter changes are integrated into existing CMOS process steps, allowing non-volatile memory production with minimal process deviations and maintained cost efficiency.
Solution Approach 2:
The ONO stack structure performs multiple functions including gate dielectric, memory storage, and charge trapping, allowing a single structure to replace what would traditionally require multiple separate components and process steps, thereby maintaining manufacturing simplicity while achieving NVM functionality.
4Area of moving object
If OTP memory solutions are used, then small size and low cost are achieved, but re-programming capability is lost
Solution Approach 1:
The patent uses parameter changes by controlling the nitride layer thickness (50-150Å) and doping characteristics to enable the trapping region to be both written and erased multiple times. This allows the cell to maintain small size while gaining MTP capability through precise parameter optimization.
Solution Approach 2:
The ONO stack uses composite material structure with oxide-nitride-oxide layers, where the nitride provides trapping capability and the oxides provide insulation and structural integrity. This composite structure enables re-programming capability while maintaining compact cell dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
CEONOS NVM cells achieve high density, low cost, and high endurance with minimal additional processing steps, enabling efficient and reliable data storage without significant deviations from standard CMOS processes, thus addressing the limitations of existing MTP NVM solutions.
Implementation Method 1
enhanced lateral field engineering for hot electron programming
Implementation Method 2
a portion of the nitride layer serves as an electrically isolated 'floating gate' that can be repeatedly programmed and erased
Data Source
AI summary
A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).