Multilayer Ceramic Capacitor Layout for Low ESL and Higher Capacitance
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Solution Overview
Problem
Multilayer ceramic capacitors face challenges with increased equivalent series inductance (ESL) and reduced capacitance due to the presence of vias, which also affect the mounting area and equivalent series resistance (ESR), necessitating a solution for miniaturization and improved performance.
Innovation Solution
A multilayer ceramic capacitor design featuring point-symmetrical internal electrodes with electrode-unformed regions, via holes, and strategically positioned connection electrodes to achieve mutual inductance cancellation, reduce ESL, and enhance capacitance, while maintaining a low thickness for compact integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a via-type capacitor structure is used to reduce mounting area, then the mounting area is reduced, but the equivalent series inductance (ESL) increases and capacitance decreases
Solution Approach 1:
The patent applies asymmetry by making the first and second internal electrodes non-symmetrical in configuration. Specifically, the first internal electrode has a first via hole while the second internal electrode has a second via hole with different positioning and connection electrode arrangements. This non-symmetrical design creates mutual inductance cancellation effects that reduce overall ESL, directly addressing the contradiction between reduced mounting area and maintained ESL performance.
2Area of stationary object
If connection electrodes are positioned close together to reduce mounting area, then mounting area is reduced, but mutual inductance cancellation effect decreases
Solution Approach 1:
The patent applies local quality by creating different spatial relationships for different electrode connections. The first connection electrode connects to the first internal electrode through a first via hole, while the second connection electrode connects to the second internal electrode through a second via hole. The positioning is optimized locally at each connection point to maximize mutual inductance cancellation while maintaining compact overall dimensions, thus reducing mounting area without sacrificing the cancellation effect.
3Length of stationary object
If internal electrodes are made smaller to reduce capacitor thickness, then capacitor thickness is reduced, but capacitance decreases
Solution Approach 1:
The patent applies dimensionality change by optimizing the lateral distribution and positioning of internal electrodes and via holes rather than simply increasing their size in one dimension. The first and second internal electrodes are positioned with specific spacing and offset arrangements that enable mutual inductance cancellation, allowing the capacitor to maintain low thickness while preserving capacitance through optimized spatial configuration rather than increased electrode size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces ESL, increases capacitance, and improves breakdown voltage, addressing the limitations of traditional via-type capacitors and enabling more efficient use in compact electronic devices.
Implementation Method 1
disposed with respective dielectric layers interposed therebetween to be point-symmetrical to each other... improve equivalent series inductance (ESL) due to a mutual inductance cancellation effect
Data Source
AI summary
A multilayer ceramic capacitor includes a body including dielectric layers and first and second internal electrodes disposed with respective dielectric layers interposed therebetween to be point-symmetrical to each other, first and second connection electrodes penetrating through the body in a direction perpendicular to the dielectric layer, and connected to the first internal electrode, third and fourth connection electrodes penetrating through the body in the direction perpendicular to the dielectric layer, and connected to the second internal electrode, first and second external electrodes disposed on both external surfaces of the body and connected to the first and second connection electrodes, and third and fourth external electrodes spaced apart from the first and second external electrodes and connected to the third and fourth connection electrodes. Each of the first and second internal electrodes includes an electrode-unformed region.