Multilayer Ceramic Chip Corner Curvature for Crack Resistance
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Solution Overview
Problem
Ceramic electronic devices, such as multilayer ceramic capacitors, face reliability issues due to stress concentration at corner portions caused by thermal expansion coefficient differences between external electrodes and the ceramic material, leading to potential cracking and degradation of insulation characteristics.
Innovation Solution
A ceramic electronic device with a multilayer chip structure having a specific curvature radius and distance relationship between corner portions and internal electrode layers, where the curvature radius R1 and distances C1, P1 satisfy the condition 0.20≤R1/√(P12−C12)≤0.80, to mitigate stress concentration and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the corner portions of the multilayer chip are made sharp (small curvature radius), then the device size is minimized, but stress concentration occurs leading to cracking and reliability degradation
Solution Approach 1:
The patent applies curvature to the corner portions of the multilayer chip by controlling the curvature radius R1 to satisfy 0.05 mm ≤ R1 ≤ 0.15 mm. This rounded corner design redistributes thermal stress away from the corners, preventing crack initiation while maintaining compact device dimensions. The specific curvature range optimizes the balance between size minimization and stress distribution.
2Reliability
If the curvature radius R1 is increased to reduce stress concentration, then crack resistance is improved, but the device dimensions increase
Solution Approach 1:
The patent changes the geometric parameter R1 (curvature radius of corner portions) to a specific range (0.05 mm ≤ R1 ≤ 0.15 mm) that optimizes stress distribution. This parameter optimization ensures sufficient crack resistance while controlling device size increase. The patent also optimizes the ratio relationship between R1 and the distance d1 to achieve balanced performance.
Solution Approach 2:
The patent applies different geometric characteristics to different regions: the corner portions have controlled curvature radius R1 for stress distribution, while the main body maintains compact dimensions. The distance d1 from corner to internal electrode layer is also specifically controlled to ensure local stress management without affecting overall device size.
3Reliability
If the distance between corner portions and internal electrode layers is increased to reduce stress concentration, then crack resistance is improved, but the internal electrode layout flexibility is reduced
Solution Approach 1:
The patent optimizes the distance parameter d1 (distance from corner portion to internal electrode layer) to satisfy 0.03 mm ≤ d1 ≤ 0.07 mm. This parameter optimization ensures sufficient separation to reduce stress concentration at corners while maintaining compact overall dimensions and preserving electrode layout flexibility for various circuit designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The specified curvature and distance relationships effectively suppress cracking and maintain the reliability of the ceramic electronic device by balancing stress distribution and insulation characteristics.
Implementation Method 1
Stress caused by thermal expansion coefficient difference between the external electrodes and the ceramic portion tends to be concentrated in corner portions of the multilayer chip
Implementation Method 2
Stress caused by thermal expansion coefficient difference between the external electrodes and the ceramic portion
Data Source
AI summary
A ceramic electronic device includes a multilayer chip including a multilayer structure, a first cover layer and a second cover layer and having a parallelepiped shape, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to a first end face and a second end face of the multilayer chip, the first end face being opposite to the second end face, the first cover layer being provided on an upper face of the multilayer structure in a stacking direction, the second cover layer being provided on a lower face of the multilayer structure, a first external electrode formed on the first end face, and a second external electrode formed on the second end face. In this structure, a relationship of 0.20≤R1/√{square root over ( )}(P12−C12)≤0.80 is satisfied.


