Ceramic Substrate Package to Prevent Sinter Joint Cracking
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Solution Overview
Problem
Semiconductor device packages experience cracking of sintering material due to mismatch in coefficients of thermal expansion (CTEs) between the semiconductor die and the copper die attach paddle, leading to degradation in thermal and electrical performance.
Innovation Solution
Utilize a direct-bonded metal (DBM) substrate with a ceramic layer that matches the CTE of the semiconductor die, and employ multi-gauge signal leads with thinner portions coupled to the die to reduce stress and eliminate cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If sintering material is used to attach semiconductor die to copper leadframe, then RoHS compliance is achieved, but cracking occurs due to CTE mismatch
Solution Approach 1:
The patent changes the substrate material from copper to ceramic with metal layers (DBC substrate), fundamentally altering the CTE parameter to match the semiconductor die. The ceramic layer has a CTE of 3-7 ppm/K, closely matching silicon carbide dies, eliminating the CTE mismatch that causes cracking while maintaining RoHS compliance through sintering material attachment.
Solution Approach 2:
The patent employs a composite DBC substrate structure consisting of a ceramic layer bonded to copper metal layers. This composite design combines the low CTE of ceramic with the high thermal conductivity of copper, achieving both CTE matching for crack prevention and effective heat dissipation, while allowing RoHS-compliant sintering material to be used for attachment.
2Reliability
If sintering material is used for die attachment, then electrical connection is achieved, but thermal dissipation performance degrades due to cracking
Solution Approach 1:
By changing the substrate material from copper to DBC ceramic substrate, the patent eliminates cracking through CTE matching. This prevents the formation of cracks that would otherwise increase electrical resistance and degrade thermal dissipation performance, maintaining both electrical connection reliability and thermal management efficiency.
Solution Approach 2:
The patent converts the potential harm of using sintering material (which can crack under thermal stress) into a benefit by using it to attach to a DBC substrate instead of copper. The sintering material now provides reliable electrical and thermal connections without cracking, because the DBC substrate's CTE matching eliminates the thermal stress that causes cracking.
3Loss of energy
If copper die attach paddle is used, then thermal conductivity is high, but CTE mismatch causes sintering material cracking
Solution Approach 1:
The patent uses a DBC composite substrate that combines ceramic (for CTE matching) and copper (for thermal conductivity). The ceramic layer provides CTE compatibility with silicon carbide dies (3-7 ppm/K vs. copper's 17 ppm/K), while the copper metal layers provide high thermal conductivity for effective heat dissipation, achieving both requirements simultaneously.
Solution Approach 2:
The DBC substrate provides different properties in different layers: the ceramic layer provides low CTE for mechanical compatibility, while the copper metal layers provide high thermal conductivity for thermal management. This local differentiation of material properties allows the single substrate to satisfy both CTE compatibility and thermal conductivity requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents or reduces degradation of thermal and electrical performance by minimizing CTE mismatch and cracking, enhancing reliability and thermal conductivity while reducing material costs.
Implementation Method 1
performing a sintering operation to couple the first surface of the semiconductor die with the metal layer and to couple the first signal lead to the second surface of the semiconductor die
Implementation Method 2
welding a second signal lead to the metal layer
Data Source
AI summary
In a general aspect, a semiconductor device package includes a ceramic substrate having a first surface and a second surface opposite the first surface, a first metal layer disposed on the first surface of the ceramic substrate, a second metal layer disposed on the second surface of the ceramic substrate, and a semiconductor die having a first surface and a second surface opposite the first surface. The first surface of the semiconductor die is coupled with the first metal layer via first sintering material. The semiconductor device package also includes a first signal lead coupled with the second surface of the semiconductor die via second sintering material, a second signal lead coupled with the second surface of the semiconductor die via third sintering material; and a third signal lead coupled with the first metal layer via a weld.