Ceramic Power-Logic Package Layout for Low-Inductance Switching
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Solution Overview
Problem
The integration of logic and power devices in semiconductor modules is challenging due to conflicting substrate requirements, where logic devices need thin conductors and power devices require thick metal for current carrying capacity.
Innovation Solution
A semiconductor package design featuring a ceramic plate with a first conductive layer, a semiconductor transistor die, an electrical connector, and a semiconductor logic die, all encapsulated with a ceramic plate, allowing for efficient interconnection and heat dissipation while accommodating both thin and thick conductor needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If logic and power devices are integrated in one module, then switching losses and parasitic inductances are reduced, but conflicting substrate requirements arise (logic needs thin conductors, power needs thick metal)
Solution Approach 1:
The conductive layer is divided into multiple segments with different thicknesses. A first conductive layer with greater thickness is provided for power device connections, while a second conductive layer with lesser thickness is provided for logic device connections. This segmentation allows each device type to receive the appropriate conductor thickness, resolving the conflict between power device current carrying requirements and logic device signal integrity requirements.
Solution Approach 2:
Different regions of the substrate are provided with different conductor thicknesses tailored to local requirements. The first conductive layer with greater thickness is localized under power devices to provide sufficient current carrying capacity, while the second conductive layer with lesser thickness is localized under logic devices to maintain signal integrity and reduce parasitic effects. This local differentiation resolves the contradiction by providing each device type with its optimal conductor thickness.
2Loss of energy
If logic and power devices are integrated in one module, then parasitic inductances are reduced, but manufacturing complexity increases due to multiple conductive layers
Solution Approach 1:
The conductive system is segmented into multiple layers deposited at different stages. The first conductive layer is deposited first to establish thick conductors for power devices, then the second conductive layer is deposited to create thin conductors for logic devices. This segmented deposition approach, while adding a manufacturing step, enables precise control over conductor thickness in different regions, ultimately reducing parasitic inductances by optimizing the interconnection structure.
Solution Approach 2:
The solution moves from a single-plane conductor to a multi-layer conductor structure, adding the vertical dimension to the conductive system. By stacking conductive layers with different thicknesses, the design achieves both thick conductors for power devices and thin conductors for logic devices within the same substrate area, reducing parasitic inductances while managing manufacturing complexity through standardized multi-layer deposition processes.
3Quantity of substance
If thick metal is used for power devices, then current carrying capacity is sufficient, but logic device requirements for thin conductors are not met
Solution Approach 1:
The conductive layer is segmented into a first conductive layer with greater thickness for power devices and a second conductive layer with lesser thickness for logic devices. This segmentation enables independent optimization of conductor thickness for each device type, ensuring that power devices receive sufficient current carrying capacity while logic devices receive appropriately thin conductors for signal integrity.
Solution Approach 2:
The substrate is designed with local quality variations, providing different conductor thicknesses in different regions. Areas underlying power devices feature the first conductive layer with greater thickness to ensure sufficient current carrying capacity, while areas underlying logic devices feature the second conductive layer with lesser thickness to meet precision requirements. This local differentiation resolves the contradiction between current carrying capacity and manufacturing precision.
Data Source
Figure 1~2
Figure 3
AI summary
A semiconductor package (10; 20; 30) comprising a ceramic plate 1, a first conductive layer (2) disposed on the ceramic plate 1, the first conductive layer (2) comprising a first portion (2.1) and a second portion (2.2), a semiconductor transistor die (3) disposed above the first portion (2.1) of the first conductive layer (2), an electrical connector (4) disposed between the semiconductor transistor die (3) and the first portion (2.1) of the first conductive layer (2), a semiconductor logic die (5) disposed on the second portion (2.2) of the first conductive layer (2), and an encapsulant (6) covering at least in part the ceramic plate (1), the first conductive layer (2), the semiconductor transistor die (3) and the semiconductor logic die (5).