Ceramic Package Substrate With Built-In Capacitor and Warpage Control
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Solution Overview
Problem
Current package substrates with built-in capacitors face challenges in achieving high capacitance due to difficulties in forming fine conductive patterns and controlling capacitance, as well as manufacturing costs and thermal expansion issues during the lamination and sintering process.
Innovation Solution
A package substrate design incorporating a ceramic substrate with a built-in capacitor structure featuring a low-temperature sintered dielectric, a redistribution structure with a high-k dielectric layer, and electrolytic or electroless plating for precise upper electrode formation, reducing misalignment and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a built-in capacitor structure is formed in the package substrate, then capacitance capacity is improved, but manufacturing complexity and cost increase due to difficulties in forming fine conductive patterns and controlling capacitance
Solution Approach 1:
The capacitor structure is merged with the package substrate by forming the lower electrode layer, dielectric layer, and upper electrode layer directly on the ceramic substrate during the substrate manufacturing process. This integration eliminates the need for separate capacitor components and reduces overall device complexity while maintaining high capacitance capacity.
Solution Approach 2:
The capacitor structure utilizes the vertical dimension of the package substrate by stacking the lower electrode layer, dielectric layer, and upper electrode layer in the thickness direction. This vertical arrangement allows for high capacitance capacity within a compact footprint, avoiding the need for complex lateral patterning.
2Ease of manufacture
If traditional lamination and sintering processes are used, then manufacturing is simplified, but thermal expansion issues and warpage occur during the process
Solution Approach 1:
The dielectric layer is formed using a low-temperature sintering process at approximately 900°C, which is lower than traditional ceramic sintering temperatures. This parameter change reduces thermal stress and prevents warpage while maintaining the dielectric properties necessary for capacitor functionality.
Solution Approach 2:
The ceramic substrate is selected to have a coefficient of thermal expansion (CTE) that matches the metal electrodes and dielectric layer. This CTE matching prevents thermal expansion mismatch during low-temperature sintering, eliminating warpage and maintaining dimensional stability throughout the manufacturing process.
3Manufacturing precision
If fine conductive patterns are formed for the capacitor electrodes, then capacitance control precision is improved, but manufacturing difficulty and cost increase
Solution Approach 1:
The lower electrode layer is formed simultaneously with the first circuit wiring layer during the initial substrate manufacturing process, before subsequent redistribution layers are added. This preliminary formation of the capacitor structure allows for precise capacitance control without requiring additional fine-patterning steps later in the manufacturing process.
Solution Approach 2:
A barrier layer is introduced between the lower electrode layer and the dielectric layer to prevent metal diffusion and ensure precise capacitance control. This intermediary layer simplifies the manufacturing process by eliminating the need for complex etching and patterning steps while maintaining precise electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-capacity capacitors with precise capacitance control, reduced manufacturing costs, and improved thermal management, preventing warpage and enhancing heat dissipation.
Implementation Method 1
a dielectric layer disposed between the ceramic substrate and the redistribution structure
Implementation Method 2
forming a ceramic substrate by sintering the plurality of conductive sheets
Implementation Method 3
electrolytic or electroless plating for precise upper electrode formation
Implementation Method 4
electrolytic or electroless plating for precise upper electrode formation
Data Source
AI summary
A package substrate includes a ceramic substrate including a plurality of first insulating layers and a first circuit wiring layer disposed in the plurality of first insulating layers, a redistribution structure disposed on an upper surface of the ceramic substrate, and including a plurality of second insulating layers and a second circuit wiring layer disposed in the plurality of second insulating layers and electrically connected to the first circuit wiring layer, and a capacitor structure provided at an interface between the ceramic substrate and the redistribution structure, and including a lower electrode layer disposed at the same vertical level as at least a portion of the first circuit wiring layer, a dielectric layer disposed between the ceramic substrate and the redistribution structure, and an upper electrode layer disposed on an upper surface of the dielectric layer.