Ceramic Substrate Power Module Layout for Lower Thermal Stress
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power modules for hybrid electric vehicles and electric vehicles face challenges in simplifying manufacturing processes, reducing costs, improving reliability, and increasing yield due to high thermal and vibration stresses on double-sided cooling modules with high-power semiconductor chips like SiC and GaN.
Innovation Solution
A power module design featuring a ceramic substrate bonded to a base plate with a semiconductor chip, a spacer, and a connecting pin, along with a bonding wire connecting the chip to a PCB substrate, which reduces thermal impact and inductance, simplifying the structure and minimizing signal transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a double-sided cooling power module with high-power semiconductor chip is used, then cooling performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the upper ceramic substrate, lower ceramic substrate, and insulation substrate into a single integrated ceramic substrate. This integration maintains the double-sided cooling function while eliminating the need for separate substrates and reducing manufacturing steps, directly resolving the contradiction between cooling performance and manufacturing complexity
Solution Approach 2:
The integrated ceramic substrate serves multiple functions simultaneously: it acts as both the upper and lower ceramic substrates for heat dissipation, and as the insulation substrate for electrical isolation. This multi-functionality achieves the cooling performance of double-sided modules while simplifying the structure and reducing manufacturing complexity
2Temperature
If multiple substrates and components are used, then cooling performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple separate substrates (upper ceramic substrate, lower ceramic substrate, insulation substrate) into one integrated ceramic substrate. This reduces the number of components and assembly steps, directly lowering manufacturing cost while preserving the heat radiation characteristics through maintained thermal pathways to both sides of the substrate
3Reliability
If complex assembly processes are used, then reliability is improved, but manufacturing time increases
Solution Approach 1:
The integrated ceramic substrate is designed with pre-formed through-holes and embedded structures that eliminate the need for post-assembly drilling and wiring. The insulation layers and conductive pathways are pre-configured during substrate manufacturing, allowing direct assembly of the semiconductor chip and connectors, thereby maintaining reliability while significantly reducing manufacturing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies manufacturing, reduces costs, enhances reliability by minimizing thermal stress and inductance, and increases product yield by stabilizing the semiconductor chip's heat transfer and electrical connections.
Implementation Method 1
a ceramic substrate bonded to an upper surface of the base plate, a semiconductor chip bonded to an upper surface of the ceramic substrate
Implementation Method 2
a bonding wire connecting terminals of the semiconductor chip to the electrode layer of the spacer
Data Source
AI summary
The present disclosure relates to a power module comprising: a base plate; a ceramic substrate bonded to the top surface of the base plate; a semiconductor chip bonded to the top surface of the ceramic substrate; a spacer bonded to the top surface of the ceramic substrate so as to be spaced apart from the semiconductor chip; a connection pin provided at an electrode layer formed on the top surface of the spacer; and a bonding wire for connecting a terminal of the semiconductor chip to the electrode layer of the spacer.


