Ceramic Circuit Substrate Roughness for Resin Delamination Resistance

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Solution Overview

Problem

The increasing operating temperature of semiconductor elements poses a challenge for ceramic circuit substrates due to delamination issues between the ceramic substrate and the mold resin, caused by differences in thermal expansion coefficients.

Innovation Solution

A ceramic circuit substrate design featuring a ceramic substrate with metal parts bonded via bonding layers, where the average length of roughness curve elements in inter-pattern regions is controlled to be not less than 40 μm, enhancing adhesion with the mold resin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the guaranteed operating temperature of semiconductor elements is increased to meet higher performance requirements, then the output and performance of semiconductor devices are improved, but the difference in thermal expansion coefficients between the ceramic circuit substrate and mold resin causes delamination

Engineering Contradiction:
Improveoutput of semiconductor elementsVSAvoidadhesion between ceramic circuit substrate and mold resin
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a roughness treatment layer on the ceramic substrate surface before bonding the metal plate and before applying mold resin. This pre-established surface roughness (with specific parameters RSm ≥ 40 μm) creates mechanical interlocking capability in advance, preventing delamination when thermal expansion differences occur during high-temperature operation. The roughness features are prepared beforehand to accommodate future thermal stress without compromising adhesion.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If a smooth surface is used on the ceramic substrate for ease of manufacturing, then the manufacturing process is simplified, but the adhesion with mold resin deteriorates under thermal expansion stress

Engineering Contradiction:
Improvesurface preparation of ceramic substrateVSAvoidadhesion between ceramic substrate and mold resin
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by creating a specific roughness treatment layer only in the inter-pattern regions between metal plate bonding areas. The surface has different properties in different locations: smooth in metal bonding areas (for good metal-to-ceramic adhesion) and rough in inter-pattern areas (for good resin adhesion). This localized surface treatment optimizes both manufacturing and reliability for their respective functions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The roughness treatment layer creates a porous or textured surface structure with controlled voids and irregularities (RSm ≥ 40 μm). This porous structure allows mold resin to penetrate and mechanically interlock with the ceramic substrate, significantly improving adhesion. The porous nature provides anchoring points that resist delamination under thermal expansion stress while maintaining manufacturing feasibility through techniques like sandblasting, chemical etching, or plasma treatment.

Inventive Principle:
Principle #31Porous materials

3Device complexity

If the thermal expansion coefficient difference between ceramic substrate and mold resin is not addressed, then the device can be manufactured simply, but delamination occurs causing conduction defects

Engineering Contradiction:
Improvestructure of ceramic circuit substrateVSAvoidabsence of delamination and conduction defects
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The roughness treatment layer acts as an intermediary between the ceramic substrate and mold resin. This intermediate layer with controlled roughness (RSm ≥ 40 μm) mediates the thermal expansion coefficient difference by providing mechanical interlocking and stress distribution. It transfers and distributes thermal stress across a larger interface area, preventing concentrated stresses that would cause delamination and subsequent conduction defects in the semiconductor device.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improved adhesion between the ceramic substrate and the mold resin reduces delamination, effectively addressing thermal expansion coefficient differences and enhancing the reliability of semiconductor devices.

Implementation Method 1

an average length RSm of roughness curve elements in the second region is not less than 40 μm

Methodology Applied
Scientific EffectMechanical interlocking:

Implementation Method 2

Improved adhesion between the ceramic substrate and the mold resin reduces delamination

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 3

The difference between the thermal expansion coefficient of the ceramic circuit substrate and the thermal expansion coefficient of the mold resin is problematic in that the mold resin delaminates from the ceramic circuit substrate

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250069994A1Ceramic circuit substrate and semiconductor device using same
Publication Date: 2025.02.27 NITERRA MATERIALS CO LTD
  • US20250069994A1 patent drawing
  • US20250069994A1 patent drawing
  • US20250069994A1 patent drawing

AI summary

A ceramic circuit substrate according to an embodiment includes a ceramic substrate and multiple metal parts. The ceramic substrate includes a first surface. The multiple metal parts are located respectively in multiple first regions of the first surface. The first surface includes a second region positioned between adjacent first regions of the multiple metal parts. An average length RSm of roughness curve elements in the second region is not less than 40 μm. The average length RSm is preferably not more than 100 μm. A maximum peak height Rp of a surface roughness curve in the second region is preferably not less than 1.0 μm. A maximum valley depth Rv of a surface roughness curve in the second region is preferably not less than 1.0 μm.