Memory Error Correction via Correlated Electron Switch Remapping
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Solution Overview
Problem
Non-volatile memory devices, such as CeRAM, are susceptible to soft errors due to ambient operating conditions and single event upsets, leading to potential permanent faults and data corruption, which existing error detection and correction methods like radiation hardening and ECC mechanisms are costly and performance-intensive.
Innovation Solution
The implementation of Correlated Electron Switch (CES) elements in memory devices, which transition between conductive and insulative states via quantum mechanical phenomena like Mott transitions, allowing for reliable detection and correction of errors by mapping impedance states to binary values, and employing a scheme that optimizes between reliability and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If radiation hardening and ECC mechanisms are used for error detection and correction, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The memory system performs self-diagnosis by comparing the state of a first memory element with a second memory element during read operations. The system automatically detects discrepancies caused by soft errors and corrects them by remapping the affected memory element, eliminating the need for external error correction codes or radiation hardening techniques.
Solution Approach 2:
The patent extracts and isolates the error detection and correction functionality into a separate remapping mechanism. Instead of using complex ECC circuits throughout the memory system, the invention removes problematic memory elements and remaps them to alternative locations, simplifying the overall system architecture while maintaining reliability.
2Reliability
If radiation hardening is implemented, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs standard, readily manufacturable memory elements rather than expensive radiation-hardened components. When soft errors occur, the system remaps the affected elements to different physical locations within the same memory array, avoiding the need for costly radiation-resistant materials or specialized manufacturing processes.
3Reliability
If ECC mechanisms are used, then reliability is improved, but performance and speed are reduced
Solution Approach 1:
The system performs error detection and remapping operations in advance during idle periods or when memory is not fully utilized. During normal read/write operations, the remapping logic is already in place, allowing data access to proceed without the performance penalty typically associated with real-time error correction calculations.
Solution Approach 2:
The patent replaces complex computational error correction mechanisms with a simpler remapping approach. Instead of performing bitwise XOR operations and syndrome calculations characteristic of ECC, the system uses direct remapping of memory element addresses, reducing the computational overhead and improving access speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of non-volatile memory systems by effectively detecting and correcting errors in-place, reducing the likelihood of soft errors and permanent faults, while maintaining memory capacity and performance.
Implementation Method 1
The implementation of Correlated Electron Switch (CES) elements in memory devices, which transition between conductive and insulative states via quantum mechanical phenomena like Mott transitions
Data Source
AI summary
Disclosed are devices and methods for storing values, symbols, parameters or conditions in memory devices as states, and subsequently mapping detected states as values, symbols parameters or conditions. In one implementation write operations may place first and second memory elements in a particular impedance state selected from between a low impedance or conductive state and a high impedance or insulative state. The high impedance or insulative state represents a first binary value or symbol while the low high impedance or conductive state represents a second binary value or symbol. Subsequently detected impedance states of the first and second memory elements may be mapped to the second binary value or symbol responsive to either of the detected impedance states being the high impedance or insulative state and the second detected impedance state.