CESL Breakthrough Etching for Precise Contact Plug Formation
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Solution Overview
Problem
As semiconductor devices approach smaller feature sizes, challenges arise in the etching process for hardmasks and etch stop layer removal, particularly in the middle end of line process, where precise control and selectivity are needed to maintain integration density and prevent damage to underlying structures.
Innovation Solution
A method involving a breakthrough process that includes dopant implantation and a wet etch stop removal process, using selective etchants and implantation of argon or fluorine to disrupt the etch stop layer, allowing for precise exposure of conductive features while minimizing lateral etching and maintaining the profile of the opening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for hardmask and etch stop layer removal, then the etching can proceed through the layers, but lateral etching occurs and damages adjacent dielectric layers and conductive features
Solution Approach 1:
The patent applies preliminary action by performing dopant implantation into the etch stop layer before the etching process. This pre-treatment modifies the etch rate profile of the etch stop layer, enabling selective removal at the bottom of the opening while protecting adjacent regions. The dopant implantation creates a localized etch rate enhancement zone that guides the etching process to proceed vertically without lateral expansion, thus preventing damage to surrounding dielectric layers and conductive features.
Solution Approach 2:
The patent implements local quality by creating a spatially varying etch rate profile through dopant implantation. The dopants are implanted in a localized region at the bottom of the opening, creating a zone with enhanced etchability. This localized modification allows the etching process to selectively remove the etch stop layer only where needed, while adjacent regions maintain their original etch resistance. The result is precise etch stop layer removal without lateral etching damage to surrounding structures.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but etching control and selectivity become more difficult to maintain
Solution Approach 1:
The patent applies parameter changes by modifying the etch rate parameter of the etch stop layer through dopant implantation. By changing the chemical composition and physical properties of the etch stop layer locally through dopant introduction, the etch rate is enhanced in the implanted region. This parameter modification enables precise control over the etching process at reduced feature sizes, allowing selective removal of the etch stop layer while maintaining protection of adjacent structures. The technique provides the necessary etching control and selectivity even as integration density increases and feature sizes decrease.
3Productivity
If standard etching processes are used, then the process is simple and fast, but the etch stop layer cannot be selectively removed without damaging underlying conductive features
Solution Approach 1:
The patent applies preliminary action by performing dopant implantation before etching to selectively modify the etch stop layer. This pre-treatment creates a localized zone with enhanced etchability at the bottom of the opening, allowing the etching process to proceed rapidly through the etch stop layer only where needed. The underlying conductive features are protected because the dopant implantation creates a selective etch rate profile that prevents lateral etching and direct contact with the conductive features. This approach maintains high etching speed while ensuring the integrity of conductive features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and selective removal of the etch stop layer, exposing conductive features without significant damage to adjacent dielectric layers, thereby supporting the formation of accurate interconnects and maintaining the integrity of the semiconductor device structure.
Implementation Method 1
performing a dopant implantation in the target region
Implementation Method 2
performing an etch to remove a portion of the etch stop layer materials in the target region
Data Source
AI summary
Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.