CESL Breakthrough Etching via Dopant Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices approach smaller feature sizes, challenges arise in the etching process for hardmasks and etch stop layer removal, particularly in the middle end of line process, where precise control and selectivity are needed to maintain integration density and prevent damage to underlying structures.
Innovation Solution
A breakthrough etching process involving dopant implantation and selective etch stop removal is employed, using physical or chemical implantation to modify the etch rate and selectivity, allowing for precise exposure of conductive features while minimizing lateral etching and maintaining the profile of the opening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for hardmask and etch stop layer removal, then the etching process can be completed, but lateral etching occurs and underlying structures may be damaged
Solution Approach 1:
The patent applies preliminary action by performing dopant implantation into the etch stop layer before the etching process. This pre-treatment modifies the etch stop layer properties in advance, creating a tailored etch rate profile that enables precise etching control and prevents lateral etching damage during subsequent processing
Solution Approach 2:
The patent changes physical and chemical parameters of the etch stop layer through dopant implantation. By introducing dopants that modify the layer's composition and structure, the etch rate becomes controllable and selective, allowing precise removal of the etch stop layer while protecting underlying conductive features from lateral etching damage
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but etching control and selectivity become more difficult
Solution Approach 1:
The patent applies local quality by creating spatially varying dopant concentrations within the etch stop layer. The dopant implantation process targets specific regions with different doses and depths, generating a localized etch rate profile that provides superior etching control and selectivity at reduced feature sizes, enabling higher integration density without sacrificing manufacturing precision
3Reliability
If etch stop layer is removed to expose conductive features, then interconnect formation is enabled, but surrounding dielectric layers may be damaged
Solution Approach 1:
The patent uses dopant implantation as an intermediary process between the etch stop layer and the etching step. The introduced dopants act as mediators that modify the etch stop layer's chemical and physical properties, creating a controlled interface that enables selective removal of the etch stop layer to expose conductive features while the modified etch profile prevents damage to surrounding dielectric layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables efficient and precise removal of etch stop layers, exposing conductive features without significant damage to surrounding dielectric layers, thus supporting the formation of reliable interconnects and maintaining the integrity of semiconductor devices at advanced technology nodes.
Implementation Method 1
performing a dopant implantation in the target region
Data Source
AI summary
Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.