Contact Etch Stop Layer for Void-Free Gate Stack Gap Filling
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Solution Overview
Problem
High aspect ratios in the gaps between gate stacks in integrated circuits lead to unsatisfactory gap filling during the formation of inter-layer dielectrics, resulting in voids, particularly in advanced technologies like 22 nm or 20 nm processes.
Innovation Solution
A method involving the formation of a contact etch stop layer (CESL) with thinner sidewall portions using directional deposition techniques, such as cluster ion beams or physical vapor deposition, to reduce the aspect ratio of the gaps and prevent void formation during the inter-layer dielectric gap filling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a contact etch stop layer (CESL) is formed on polysilicon gates, then the gates can be replaced by metal gates with optimized band-edge work functions, but the aspect ratio of the gaps between gate stacks increases
Solution Approach 1:
The CESL is formed with non-uniform thickness: thicker at the bottom (on substrate) and thinner on the sidewalls of gate spacers. This local variation in thickness reduces the gap aspect ratio while maintaining the gate replacement functionality, resolving the contradiction between reliability and aspect ratio.
2Ease of manufacture
If high-density plasma (HDP) processes are used for ILD gap filling, then the process is widely adopted, but voids are formed in the gaps due to unsatisfactory gap filling capability
Solution Approach 1:
The CESL thickness parameters are specifically optimized: bottom portion thickness is greater than sidewall portion thickness. This parameter change enables better ILD gap filling by reducing the effective gap height, preventing void formation while maintaining HDP process compatibility.
3Reliability
If replacement gates with great heights are used, then band-edge work functions can be achieved, but the aspect ratios of the gaps between gate stacks become particularly high
Solution Approach 1:
The CESL thickness varies in the vertical dimension: thicker at the bottom and thinner on sidewalls. This dimensional variation effectively reduces the gap aspect ratio while preserving the tall gate structure needed for work function optimization, resolving the contradiction between reliability and aspect ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced aspect ratio of the gaps minimizes the likelihood of voids during the gap-filling process, enhancing the reliability and performance of MOS devices, especially in the gate-last approach where gate stacks are of great height.
Implementation Method 1
directional deposition techniques, such as cluster ion beams or physical vapor deposition
Data Source
AI summary
A method of forming an integrated circuit structure includes providing a gate stack and a gate spacer on a sidewall of the gate stack. A contact etch stop layer (CESL) is formed overlying the gate spacer and the gate stack. The CESL includes a top portion over the gate stack, a bottom portion lower than the top portion, and a sidewall portion over a sidewall of the gate spacer. The top and bottom portions are spaced apart from each other by the sidewall portion. The sidewall portion has a thickness less than a thickness of the top portion or a thickness of the bottom portion.