CESoP Subrate Clock Synchronization for Co-Directional DTE/DCE Timing
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Solution Overview
Problem
The challenge in migrating legacy DCE/DTE interfaces to IP networks is synchronizing clocks between endpoints, particularly in co-directional timing scenarios where traditional CESoP devices rely on a master clock, failing to maintain synchronization when subrate clocks are not derived from a common source.
Innovation Solution
The implementation of a system using phase-locked loops (PLLs) to phase-lock incoming subrate clocks from DCE or DTE devices, enabling synchronization in both directions of transmission, and utilizing a series of three PLLs to achieve end-to-end synchronization in co-directional clocking modes, allowing CESoP devices to synchronize with connected devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CESoP devices use a master clock for timing, then clock synchronization is maintained in counter-directional timing mode, but synchronization fails in co-directional timing mode where subrate clocks are not derived from the master device
Solution Approach 1:
The system dynamically adapts its clocking behavior based on the timing mode. In co-directional timing mode, each endpoint independently recovers and uses its own clock, whereas in counter-directional mode, one endpoint acts as master. This dynamic adaptation allows the system to maintain synchronization across both timing modes without requiring separate hardware systems.
Solution Approach 2:
The invention changes the clocking parameters and relationships between endpoints based on the operating mode. By adjusting how clocks are derived, distributed, and synchronized depending on whether the system is in co-directional or counter-directional timing mode, the system resolves the contradiction between maintaining reliability across different timing configurations.
2Adaptability or versatility
If independent clocking schemes are used in co-directional timing mode, then adaptability and independence between endpoints are improved, but clock synchronization between endpoints deteriorates
Solution Approach 1:
The system implements feedback mechanisms where each endpoint monitors the timing relationship with its peer and adjusts its clock recovery and generation accordingly. This feedback loop ensures that even with independent clocking schemes, both endpoints remain synchronized through continuous monitoring and adjustment of timing parameters.
Solution Approach 2:
The invention introduces intermediary timing mechanisms and protocols that mediate between the independent clock sources at each endpoint. These intermediaries facilitate coordination and synchronization without requiring one endpoint to dominate as a master clock, thus preserving independence while maintaining synchronization.
3Productivity
If legacy DCE/DTE interfaces are migrated to IP networks using CESoP, then network modernization and cost reduction are achieved, but clock synchronization complexity increases
Solution Approach 1:
The system implements a universal clock synchronization mechanism that handles both co-directional and counter-directional timing modes through the same hardware platform. This multi-functionality allows the system to modernize legacy interfaces to IP networks using CESoP while managing clock synchronization complexity through a unified approach rather than requiring separate systems for different timing modes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures reliable synchronization between DTE and DCE devices in co-directional clocking scenarios, maintaining data integrity and availability by using extra PLL technology to upscale subrate input clocks, facilitating co-directional clocking schemes and maintaining endpoint synchronization.
Implementation Method 1
A first phase-locked loop converter, the first phase-locked loop converter receiving a signal having a first bit rate from a device
Data Source
AI summary
A system for locking subrate clocks includes a module that the system phase-locks an incoming subrate clock from a Data Communication Equipment device. A Circuit Emulation Services over Packet transmission network is used to connect the Data Communications Equipment device to a Data Terminal Equipment device. Synchronization between end points is maintained by the system.