CFAR OS Detection Hardware with Variable K Value
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Solution Overview
Problem
Existing CFAR-OS detectors face challenges in real-time sorting of data samples for target detection, especially at high frequencies, and struggle with edge cells due to computational costs and invalid outputs near the beginning or end of data samples, where insufficient neighboring samples lead to invalid threshold calculations.
Innovation Solution
A method that uses a variable K value scaled based on the number of available data samples in the shift register, allowing for valid target detection even at edge cells by adjusting the Kth ranked noise level calculation, and incorporates a serial shift register with two incoming and two outgoing data samples per cycle to handle guard cells and reduce hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed K value is used in CFAR-OS detection, then the detection threshold can be calculated consistently, but edge cells produce invalid outputs due to insufficient neighboring samples
Solution Approach 1:
The patent applies dynamics by making the K value variable rather than fixed. The K value is dynamically adjusted based on the position of the cell under test (CUT) within the shift register - using a first K value for edge cells and a second K value for central cells. This dynamic adaptation allows the system to handle edge cells with insufficient neighboring samples while maintaining consistent detection performance across all cell positions.
2Measurement precision
If real-time sorting of data samples is performed for CFAR-OS detection, then target detection accuracy is improved, but computational cost and hardware complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the sorting operation into two distinct phases: an offline phase where data samples are sorted and stored in a lookup table (LUT), and an online phase where the pre-sorted LUT is quickly accessed during detection. This segmentation moves the computationally intensive sorting operation out of real-time processing, significantly reducing hardware complexity while maintaining detection accuracy.
Solution Approach 2:
The patent applies preliminary action by performing the data sample sorting operation beforehand during system initialization or offline processing, and storing the sorted results in a lookup table. This preliminary sorting eliminates the need for complex real-time sorting circuitry during actual target detection, reducing hardware complexity while preserving measurement precision.
3Measurement precision
If a large window of neighboring cells is used for noise floor estimation, then detection accuracy is improved, but hardware resources and computational load increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing sorted data samples from the neighboring cells in a lookup table during offline processing. During real-time detection, the system simply accesses the pre-processed LUT to obtain the Kth ranked value for noise floor estimation, eliminating the need for complex real-time sorting and reducing hardware resource requirements while maintaining accuracy.
Solution Approach 2:
The patent applies copying by creating a lookup table that stores pre-sorted data samples from neighboring cells. Instead of performing complex sorting operations in real-time, the system copies pre-computed sorted values from the LUT during detection, significantly reducing computational load and hardware resource requirements while maintaining noise floor estimation accuracy.
Data Source
AI summary
In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.