2D Semiconductor Slabs in CFET Circuits for Footprint Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a challenge in reducing the footprint size of CMOS cell circuits while maintaining control over leakage currents and improving current flow, as conventional methods like FinFETs and Gate-All-Around devices face limitations in gate length scaling due to quantum tunneling effects.
Innovation Solution
The use of vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) cell circuits, where N-type and P-type channel structures are formed using MX2-type compounds, allowing for reduced gate lengths without increasing leakage currents, by employing elongated monolayers of 2D materials stacked to form each semiconductor channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate length is reduced to shrink cell circuit footprint, then area is reduced, but leakage current increases and on/off control deteriorates
Solution Approach 1:
The patent transitions from planar FET architecture to vertically stacked FETs (CFETs) where N-type and P-type transistors are stacked in the vertical dimension. This allows the cell circuit footprint in the horizontal plane to be reduced while maintaining adequate gate length in the vertical direction to control leakage current. The vertical stacking enables three-dimensional integration without sacrificing the gate length needed for reliable on/off control.
Solution Approach 2:
The patent employs FinFET channel structures with composite material compositions, including semiconductor materials such as silicon-germanium (SiGe) in the channel region. These composite materials enable improved carrier mobility and threshold voltage control, allowing shorter gate lengths to be used effectively while maintaining low leakage current. The engineered material composition optimizes the trade-off between drive current and leakage control.
2Reliability
If gate length is reduced to improve current flow control, then on/off control improves, but quantum tunneling effects increase causing leakage
Solution Approach 1:
By stacking FETs vertically, the patent maintains sufficient gate length in the vertical dimension even as horizontal dimensions are reduced. The vertical gate structure provides adequate channel length to suppress quantum tunneling effects while still achieving improved current flow control through the FinFET geometry and high-k dielectric materials.
Solution Approach 2:
The patent changes material parameters by introducing high-k dielectric materials in the gate stack and engineered semiconductor compositions in the channel. These parameter changes allow for effective gate control with reduced gate length while suppressing quantum tunneling through improved electric field confinement and adjusted band structure in the semiconductor materials.
3Area of stationary object
If conventional FinFET scaling is continued to reduce footprint, then area reduction is achieved, but quantum tunneling limits further scaling
Solution Approach 1:
The patent resolves the scaling limitation by moving to vertical stacking of FETs, exploiting the third dimension (vertical direction) for integration. This CFET architecture allows continued footprint reduction in the horizontal plane without further shrinking gate length, as the vertical gate structure provides sufficient channel length control. The harmful quantum tunneling effect is mitigated by maintaining adequate vertical gate length while achieving high density through stacking.
Solution Approach 2:
The patent segments the complementary FET pair into separate vertical stacks, with N-type and P-type transistors stacked independently. This segmentation allows each transistor to have optimized gate length and channel structure for its specific function, enabling both to achieve low leakage control without being constrained by planar layout limitations that would force further gate length reduction.
Data Source
AI summary
Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.