CFET 3T Gain Cell Layout for Memory Scaling and Retention
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Solution Overview
Problem
The challenge lies in scaling memory devices efficiently, as embedded high-capacity memories occupy significant silicon area and traditional SRAM faces scalability issues, while DRAM, particularly 3TGC, cannot fully benefit from CFET technology due to the use of all nMOS or all pMOS transistors, limiting area scaling and performance.
Innovation Solution
A CFET-friendly 3TGC design is implemented with a mix of nMOS and pMOS transistors to exploit 3D CFET processes, achieving 50% area scaling and improving retention time by adding capacitance through a dummy gate or polysilicon node, allowing for efficient use in System on a Chip (SoC) applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional 3TGC designs use all nMOS or all pMOS transistors, then the device structure is simple, but area scaling is limited and CFET technology benefits cannot be fully exploited
Solution Approach 1:
The patent applies asymmetry by using a mixed transistor configuration with two nMOS transistors and one pMOS transistor instead of symmetric all-nMOS or all-pMOS designs. This asymmetric composition enables 50% area scaling by effectively utilizing CFET vertical stacking, where the pMOS transistor is positioned in the backside layer beneath the nMOS transistors, optimizing space utilization and breaking the symmetry constraint of traditional designs.
Solution Approach 2:
The patent transitions from planar 2D layout to 3D vertical stacking by implementing CFET technology. The pMOS transistor is placed in the backside layer below the nMOS transistors, utilizing the vertical dimension to reduce footprint area. This dimensional change enables denser packing and achieves the targeted 50% area scaling while maintaining electrical performance.
2Quantity of substance
If memory density is increased to meet on-chip cache demands, then capacity requirements are satisfied, but silicon area consumption increases
Solution Approach 1:
The patent implements nesting by placing the pMOS transistor within the vertical footprint of the nMOS transistors through CFET stacking. The backside pMOS device is nested beneath the frontside nMOS devices, allowing multiple transistors to occupy the same lateral footprint. This nested arrangement increases memory capacity without proportionally increasing silicon area, achieving higher density.
Solution Approach 2:
By transitioning to 3D vertical stacking with CFET, the patent adds the vertical dimension to the traditional planar layout. This enables more transistors to be packed into the same footprint by utilizing z-axis stacking, thereby increasing memory capacity while constraining lateral area expansion.
3Duration of action of stationary object
If retention time is improved by adding capacitance, then data hold capability increases, but additional capacitor processes are required
Solution Approach 1:
The patent applies multi-functionality by having the dummy gate structure serve dual purposes: as a control element for the pMOS transistor and as a capacitance source for improving retention. The polysilicon layer that forms the dummy gate also creates parasitic capacitance at the storage node, eliminating the need for separate capacitor structures and associated fabrication processes.
Solution Approach 2:
The dummy gate structure provides self-service by automatically generating the required capacitance for retention without requiring additional dedicated capacitor components. The inherent parasitic capacitance formed by the dummy gate's physical structure serves the retention function, allowing the device to improve its own performance using its existing structural elements.
Data Source
AI summary
Embodiments herein relate to a three-transistor gain cell which is provided using a complementary field-effect transistor device to achieve scaling. The cell includes an n-type layer arranged above a p-type layer. In one implementation, two nMOS transistors are arranged above one pMOS transistor and a conductive path is provided to connect the gate of one of the nMOS transistors to a storage node in the p-type layer, where the storage node is coupled to a drain of the pMOS transistor. In another implementation, one nMOS transistor is arranged above two pMOS transistors and a conductive path is provided to connect the gate of one of the pMOS transistors to a storage node in the n-type layer, where the storage node is coupled to a source of the nMOS transistor.