CFET Airgap Between Source/Drain Regions
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Solution Overview
Problem
Capacitance coupling in complementary field effect transistors (CFETs) is excessive, leading to potential false turn-on or read/write disturb in SRAM, affecting stability and performance.
Innovation Solution
A method involving the formation of a nanosheet stack with alternating layers of semiconductor materials, creating an airgap between the source/drain regions of p-type and n-type field effect transistors to reduce capacitance coupling, including forming a nanosheet stack, depositing sacrificial materials, and removing them to define the airgap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If source/drain regions of pFET and nFET are placed in direct contact in CFET, then device area is reduced through stacking, but capacitance coupling between the two devices increases excessively
Solution Approach 1:
A sacrificial material layer is deposited between the source/drain regions of the pFET and nFET. This intermediary layer is then selectively removed to create an airgap, which acts as a mediator that physically separates the two devices while maintaining their stacked configuration. The airgap reduces capacitance coupling by eliminating direct electrical contact and reducing the electric field interaction between the source/drain regions.
Solution Approach 2:
The harmful dielectric material that would normally fill the space between source/drain regions is extracted and removed. By selectively removing the sacrificial material, an airgap is created that extracts the problematic dielectric medium, thereby reducing the capacitance coupling between the stacked devices while preserving the area benefits of the stacked configuration.
2Strength
If dielectric material is used to fill the space between source/drain regions, then structural support is provided, but capacitance coupling increases due to the dielectric's electrical properties
Solution Approach 1:
The sacrificial material serves as a temporary intermediary that provides structural support during fabrication. After the source/drain regions are formed, the sacrificial material is removed to create an airgap, replacing the dielectric intermediary with an air intermediary that provides minimal structural support but significantly reduces capacitance coupling.
Solution Approach 2:
The dielectric constant of the material between source/drain regions is changed from a high value (dielectric material) to a low value (air). This parameter change in the material property directly reduces the capacitance coupling while the airgap geometry is designed to maintain adequate structural support.
Data Source
AI summary
A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.