CFET Channel Layout With Angled Tiers for Gate Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional complementary field effect transistors (CFETs) face challenges in accessing terminals, independent gate fabrication, and design constraints such as aligned contact poly pitch (CPP) for top and bottom devices.
Innovation Solution
The CFET device features misaligned top and bottom channels, allowing improved access to terminals and independent gate control. Vertical connection structures connect the bottom and top transistor structures, enabling efficient routing and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the top and bottom FET channels are aligned (parallel to each other) in a conventional CFET, then the device structure is simple and fabrication is easier, but the access to terminals of the bottom device from the top becomes difficult and independent gate fabrication becomes challenging
Solution Approach 1:
The patent applies asymmetry by arranging the top and bottom transistor channels at an angle (e.g., 90 degrees) relative to each other rather than in parallel alignment. This asymmetric configuration enables independent gate access and improved terminal connectivity while maintaining compact footprint, directly resolving the contradiction between fabrication simplicity and terminal accessibility.
2Device complexity
If the top and bottom devices have the same contacted poly pitch (CPP) in conventional CFETs, then the design is symmetric and layout is simpler, but independent gate control and routing flexibility are limited
Solution Approach 1:
The patent employs asymmetric channel orientation where top and bottom transistors are rotated relative to each other (e.g., 90-degree angle), breaking the symmetry of conventional designs. This enables different contacted poly pitch configurations for top and bottom devices, providing enhanced routing flexibility and independent gate control while maintaining manageable design complexity.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
The present disclosure relates to a complementary field effect transistor, CFET, device (1) and to a method of fabricating a CFET device (1). The CFET device (1) comprises a bottom transistor structure (10) arranged in a bottom tier of the CFET device (1), wherein the bottom transistor structure (10) comprises: at least one bottom channel (11), and a bottom gate (12) arranged to electrically control the at least one bottom channel (11). The CFET device (1) further comprises a top transistor structure (20) arranged in a top tier of the CFET device (1) above the bottom tier, wherein the top transistor structure (20) comprises: at least one top channel (21), and top gate arranged to electrically control the at least one top channel (21); wherein the at least one top channel (21) is arranged at an angle to the at least one bottom channel (11).