CFET Standard Cell Layout With Asymmetric Contacts for Transistor Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of three-dimensional transistors in semiconductor integrated circuits faces challenges due to unbalanced characteristics between p-type and n-type FETs, leading to increased power consumption and resistance differences in power supply routes.
Innovation Solution
A layout structure for standard cells using complementary FETs (CFETs) is implemented, where the size and length of contacts connecting power supply lines to transistors are optimized to balance the resistance and characteristics of p-type and n-type transistors, with longer and larger contacts in the depth direction for n-type transistors to match the resistance of p-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional transistors (CFETs) are stacked vertically with p-type and n-type FETs at different distances from wiring layers, then integration density is improved, but contact length differences cause transistor characteristic imbalance
Solution Approach 1:
The patent applies asymmetry by making the second contact (for n-type FET) longer and larger in planar view than the first contact (for p-type FET). This asymmetric design compensates for the different distances of p-type and n-type FETs from the wiring layers, balancing the resistance characteristics and achieving equal transistor performance despite the vertical stacking asymmetry
Solution Approach 2:
The patent changes the physical parameters of the contacts - specifically the length in the depth direction and the size in planar view. By adjusting these parameters, the resistance of the longer second contact is increased to match the resistance of the shorter first contact, thereby balancing the transistor characteristics while maintaining high integration density
2Reliability
If contact lengths in the depth direction are made equal for both p-type and n-type FETs, then transistor characteristic balance is improved, but integration density and vertical utilization are reduced
Solution Approach 1:
The patent resolves the contradiction by moving from a one-dimensional (depth direction only) contact length consideration to a two-dimensional solution that includes both depth direction length and planar view size. The second contact is made longer in the depth direction and larger in planar view, which balances resistance without limiting vertical stacking potential, thus maintaining high integration density while achieving transistor characteristic balance
3Productivity
If scaling down of gate length is continued, then integration degree and operating speed are improved, but off current increases and power consumption rises
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional vertically stacked CFETs. This dimensional change allows continued scaling and improved integration density while the vertical structure provides better control over the channel, reducing off-current and power consumption compared to conventional planar devices at the same scaling node
Data Source
AI summary
A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.