CFET Source-Drain Epitaxy with Blocking Layers and Level Sequencing
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Solution Overview
Problem
The challenge in manufacturing complementary field effect transistors (CFETs) lies in simultaneously performing upper and lower level epitaxial growths of source and drain materials, as the upper level epitaxy can block access to the lower level, requiring a sequential approach to ensure proper integration and manufacturability.
Innovation Solution
A method involving the sequential epitaxial growth of source and drain materials in CFETs, starting with the lower level and then the upper level, using blocking materials and silicon oxidation to selectively expose and protect areas for growth, ensuring different materials and dopants are used for each level without simultaneous growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If upper level epitaxial growth is performed first, then upper level source and drain materials can be formed, but the upper level epitaxy blocks access to the lower level preventing lower level growth
Solution Approach 1:
The manufacturing process is segmented into distinct sequential stages: first forming upper level source/drain structures with blocking materials deposited, then removing blocking materials to expose lower level regions for epitaxial growth. This segmentation allows each level to be processed independently without interference, resolving the accessibility conflict between upper and lower levels.
Solution Approach 2:
Blocking materials are deposited in advance on the upper level before lower level processing begins. This preliminary action prevents premature epitaxial growth on the upper level while enabling lower level source/drain formation to proceed first, establishing the correct growth sequence without requiring simultaneous multi-level access.
2Reliability
If sequential epitaxial growth is used to avoid blocking issues, then proper integration is achieved, but manufacturing time and process steps increase
Solution Approach 1:
Blocking materials serve as intermediary elements that temporarily occupy the upper level regions during lower level processing. These intermediaries enable the sequential growth approach by preventing unwanted epitaxial growth on the upper level while allowing lower level source/drain formation to complete, ensuring proper integration without requiring complex simultaneous multi-level processing.
Solution Approach 2:
The process utilizes parameter changes in material properties - specifically the selective removal of blocking materials through etching processes. By changing the physical state and composition of blocking materials from deposited films to removed residues, the process enables transition between upper and lower level processing stages, maintaining reliability while managing manufacturing time through efficient parameter transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables realistic unit processes for CFET manufacturing, allowing for robust integration and effective formation of source and drain components, enhancing transistor performance by enabling different material epitaxy on each level without interference.
Implementation Method 1
oxidizing silicon at a surface of an upper level of the unfinished CFET structure to provide one or more SiO2 protective layers in the upper level
Implementation Method 2
performing silicon epitaxial growth in the lower level of the unfinished CFET structure including at least a portion of the lateral recess to form the portion of one of the source and the drain
Data Source
AI summary
A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.