CFET Wafer Bonding and Local Interconnects for Higher Density
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Solution Overview
Problem
Current technologies face challenges in increasing transistor density in integrated circuits, particularly in forming complementary Field-Effect Transistors (CFETs) with efficient local interconnects that allow for flexible material and structural variations between upper and lower transistors.
Innovation Solution
The formation of CFETs through sequential or parallel processes, enabling the use of different semiconductor materials and structures for upper and lower transistors, including Gate-All-Around (GAA) and Fin Field-Effect Transistors (FinFETs), with local interconnects that allow for various orientations and conductivity types, and the use of bonding processes like face-to-back and back-to-back to create composite wafers with optimized transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar transistor structures are used, then manufacturing process is simple, but transistor density cannot meet increasing demands
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically stacked CFET structures. Multiple transistor channels are stacked vertically to increase the number of transistors per footprint area, thereby achieving higher transistor density without proportionally increasing the lateral device area.
Solution Approach 2:
The patent implements nested transistor structures where upper and lower transistors are vertically stacked and interconnected through shared source/drain regions. The upper transistor is effectively nested above the lower transistor, with both transistors sharing common structural elements like the semiconductor substrate and interconnect layers, enabling compact high-density integration.
2Adaptability or versatility
If identical structures are used for upper and lower transistors, then manufacturing is simplified, but performance optimization is limited
Solution Approach 1:
The patent applies different semiconductor materials, doping types, and structural configurations to upper and lower transistors based on their specific performance requirements. For example, the lower transistor may use one material system while the upper transistor uses another, allowing each transistor to be optimized for its particular function without requiring identical manufacturing steps for both.
Solution Approach 2:
The patent divides the transistor formation process into separate sequential steps for upper and lower transistors. This segmentation allows independent optimization of each transistor's materials and structures while still using a common manufacturing platform, balancing manufacturing feasibility with performance customization.
3Productivity
If vertically stacked CFET structures are implemented, then transistor density increases, but interconnect formation complexity increases
Solution Approach 1:
The patent merges the source/drain regions of upper and lower transistors into shared interconnect structures. The source/drain regions serve dual purposes as both active transistor components and as interconnect elements, reducing the need for separate interconnect layers and simplifying the overall interconnect architecture despite the vertical stacking.
Solution Approach 2:
The patent designs source/drain regions to perform multiple functions: serving as the active source/drain contact for transistor operation, providing vertical electrical interconnection between upper and lower transistors, and acting as part of the overall interconnect network. This multi-functionality reduces the total number of interconnect elements needed.
Data Source
AI summary
A method includes forming a lower transistor in a lower wafer, wherein the lower transistor includes a lower source/drain region, forming a contact plug electrically connecting to the lower source/drain region, and forming a metal line over the lower transistor. A first portion of the metal line is vertically aligned to the lower source/drain region. The method further includes bonding an upper wafer to the lower wafer, and forming an upper transistor in the upper wafer. The upper transistor includes an upper source/drain region, and is vertically aligned to a second portion of the metal line. A first interconnect structure is formed on the lower wafer and electrically connecting to the lower transistor. A second interconnect structure is formed on the upper wafer and electrically connecting to the upper transistor.