CFET Bonding Structure for Low-Thermal Vertical Integration
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Solution Overview
Problem
The integration of complementary FET (CFET) devices in semiconductor manufacturing is challenging due to complex manufacturing processes, particularly when vertically stacking transistors, which can lead to damage from thermal processes.
Innovation Solution
The formation of CFET structures involves separately forming n-type and p-type transistors on different wafers and bonding them together using hybrid bonding techniques, including dielectric-to-dielectric and metal-to-metal bonding, to simplify the manufacturing process and maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If n-type and p-type transistors are vertically stacked to form CFET structures, then the effective channel width is maximized, but the manufacturing process becomes more complex and vulnerable to thermal damage
Solution Approach 1:
The CFET structure is divided into two separate wafers: a first wafer containing the n-type transistor and a second wafer containing the p-type transistor. These wafers are manufactured independently and then bonded together, segmenting the complex vertical stacking process into manageable separate fabrication steps that can be processed independently without thermal interference.
Solution Approach 2:
The n-type and p-type transistors are pre-formed on separate wafers before being combined. This preliminary action allows each transistor type to be fully fabricated and tested independently, with all necessary structures (channels, gates, source/drain regions) already in place before the bonding step, simplifying the overall integration process.
2Reliability
If transistors are vertically stacked in CFET structures, then device performance is improved, but thermal processes during integration cause damage
Solution Approach 1:
By segmenting the CFET structure into two separately fabricated wafers that are cold-bonded together, the invention eliminates the need for high-temperature thermal processes that would be required if both transistor types were fabricated and integrated in a single sequential process on one wafer.
Solution Approach 2:
A bonding interface acts as an intermediary between the n-type and p-type transistors, allowing the two separately fabricated devices to be connected without direct thermal interaction. The bonding process occurs at lower temperatures compared to traditional thermal integration methods, protecting the sensitive transistor structures from thermal damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process while preserving the performance of the resulting CFET devices by avoiding damage from thermal processes during integration.
Implementation Method 1
bonding them together using hybrid bonding techniques, including dielectric-to-dielectric and metal-to-metal bonding
Data Source
AI summary
A semiconductor structure and a formation method are provided. The semiconductor structure includes a first transistor, and the first transistor includes a first channel layer and a first gate structure. The semiconductor transistor further includes a second transistor. The second transistor includes a second channel layer and a second gate structure. The semiconductor transistor further includes a bonding structure vertically sandwiched between the first transistor and the second transistor. The bonding structure includes a first dielectric bonding layer attached to the first gate structure and a first conductive bonding structure formed through the first dielectric bonding layer. The bonding structure further includes a second dielectric bonding layer attached to the first dielectric bonding layer and the second gate structure and a second conductive bonding structure formed through the second dielectric bonding layer and bonded to the first conductive bonding structure.