CFET Cell Layout With Bottom Routing for Contact Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional complementary field effect transistor (CFET) devices face challenges in connecting bottom device contacts due to shadowing by top devices, leading to difficulties in signal routing and power distribution, especially when trying to access bottom contacts from the edges of the standard cell.
Innovation Solution
A CFET cell design featuring top signal routing lines in a first metal layer and bottom signal routing lines in a second metal layer, allowing for dedicated access to bottom transistor structures without enlarging the cell, and enabling easier fabrication by simplifying signal routing and power rail connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bottom device contacts are accessed from the edges of the standard cell, then connectivity to bottom transistor structures is achieved, but the cell area increases and routing complexity increases
Solution Approach 1:
The patent introduces a new dimension by forming bottom signal routing lines in a second metal layer below the first tier, allowing vertical access to bottom device contacts through the substrate rather than lateral edge routing. This dimensional change enables compact cell layout while maintaining full connectivity to bottom transistor structures.
2Reliability
If tall vias are used to connect bottom contacts from top metal level, then connectivity is achieved, but manufacturing precision requirements increase and fabrication difficulty increases
Solution Approach 1:
Instead of routing signals from the top metal level down to bottom contacts using tall vias, the patent inverts the approach by forming bottom signal routing lines in a second metal layer below the first tier and connecting them directly to bottom device contacts at the same level. This eliminates the need for tall vias and reduces alignment precision requirements.
3Power
If top power rail occupies one edge of the standard cell, then power distribution is achieved, but access to bottom device contacts is blocked and routing flexibility decreases
Solution Approach 1:
The patent segments the power distribution system by separating top power rail connections from bottom signal routing. Bottom signal routing lines in the second metal layer can access bottom device contacts independently of the top power rail position, enabling flexible routing configurations regardless of power rail placement.
4Reliability
If complex side routing structures are used to access bottom contacts, then connectivity is achieved, but device complexity increases and fabrication ease decreases
Solution Approach 1:
The patent simplifies routing by moving bottom signal routing to a second metal layer below the first tier, creating a dedicated routing plane for bottom device connections. This eliminates the need for complex three-dimensional side routing structures and reduces overall device complexity while maintaining full connectivity.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
The disclosure relates to a complementary field effect transistor (CFET) cell (10). The CFET cell (10) comprises: a first transistor structure (11) arranged in a first tier of the CFET cell (10); a second transistor structure (12) arranged in a second tier of the CFET cell (10) above the first tier; a set of top signal routing lines (15) formed in a first metal layer above the second tier and connected to the first and the second transistor structure (11, 12) from above; and at least one bottom signal routing line (16) formed in a second metal layer below the first tier and connected to the first transistor structure (11) from below. The disclosure relates to a method of fabricating a CFET cell (10).