Compact CFET Cell Layout With 3D Nanosheet Stacking
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in scaling transistors beyond single-digit nanometer nodes, particularly in achieving higher transistor density and efficiency, as traditional two-dimensional approaches reach limitations, prompting the need for three-dimensional integration methods.
Innovation Solution
The method involves 3D stacking with source and drain extensions using 3D channel nanosheet core formation and self-aligned metal extensions for horizontal device integration, enabling the fabrication of high-density 3D complementary field-effect transistors (CFET) and complementary metal-oxide semiconductor (CMOS) devices with reduced process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional two-dimensional fabrication approaches are used, then manufacturing processes are simpler and easier to implement, but transistor density and circuit capacity are limited
Solution Approach 1:
The patent transitions from traditional two-dimensional planar fabrication to three-dimensional vertical stacking by forming alternating semiconductor layers (first and second semiconductor layers) and dielectric layers in a stacked configuration. This dimensional change enables multiple transistor channels to be integrated vertically within the same footprint area, dramatically increasing transistor density while managing fabrication complexity through systematic layer-by-layer construction
2Productivity
If three-dimensional stacking is implemented to increase transistor density, then circuit capacity improves, but fabrication process complexity increases significantly
Solution Approach 1:
The patent performs preliminary actions by pre-forming the stacked semiconductor and dielectric layer structure before introducing gate electrodes and source/drain regions. The alternating layers are constructed in advance with precise alignment, and spacer structures are formed beforehand to define subsequent etching regions. This preliminary structuring simplifies later fabrication steps by establishing a ready-made template for device formation
Solution Approach 2:
The fabrication process is segmented into distinct modular stages: (1) forming alternating semiconductor and dielectric layers, (2) removing portions to expose sidewalls, (3) forming epitaxial structures, and (4) forming metal structures. Each stage operates independently on specific layers or regions, allowing parallel processing and reducing overall process complexity despite the three-dimensional architecture
3Manufacturing precision
If more fabrication steps are used to achieve high-density 3D devices, then device performance improves, but manufacturing time and cost increase
Solution Approach 1:
The patent merges multiple fabrication operations into combined steps: alternating semiconductor and dielectric layers are deposited in a single sequential process, multiple epitaxial structures are formed simultaneously in the same reaction chamber, and metal structures are patterned and deposited in unified steps. This merging reduces the total number of separate process cycles, decreasing fabrication time while maintaining the precision required for high-density three-dimensional device structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density and efficiency by allowing for vertical growth of devices, reducing fabrication steps, and enabling high-density circuit formation at lower costs, thereby overcoming scaling limitations in traditional 2D fabrication.
Implementation Method 1
forming, through the removed second portion of the first stack, a pair of first epitaxial structures in contact with a lower one of the second semiconductor layers, respectively. The method includes forming, through the removed second portion of the first stack, a pair of second epitaxial structures in contact with an upper one of the second semiconductor layers, respectively.
Data Source
AI summary
Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first stack over a substrate, including first dielectric layers and second dielectric layers alternately stacked on top of one another. The method includes replacing a first portion of the first stack with a second stack including first semiconductor layers and second semiconductor layers alternately stacked on top of one another. The method includes removing a second portion of the first stack to expose sidewalls of each of the second semiconductor layers, respectively. The method includes forming, through the removed second portion of the first stack, a pair of first epitaxial structures in contact with a lower one of the second semiconductor layers, respectively. The method includes forming, through the removed second portion of the first stack, a pair of second epitaxial structures in contact with an upper one of the second semiconductor layers, respectively.