CFET Channel Structure Using Epitaxy to Expand Effective Width
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Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes to improve integration density, challenges arise in maintaining effective channel width and tuning device performance in Complementary Field-Effect Transistors (CFETs).
Innovation Solution
The CFET structure and method involve modifying the channel regions by forming vertically stacked FETs with semiconductor nanostructures, using a multi-layer stack with silicon and silicon germanium layers, and employing selective epitaxy to grow silicon or SiGe layers, resulting in increased effective channel width and improved performance tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then integration density is improved, but effective channel width is reduced
Solution Approach 1:
The patent transitions from planar FETs to vertically stacked 3D FETs, utilizing the vertical dimension to increase effective channel width without expanding the horizontal footprint. Multiple channel regions are stacked vertically, allowing the device to maintain high integration density while achieving larger total channel width through the third dimension.
Solution Approach 2:
The patent implements nested structures where gate electrodes and channel regions are interleaved in vertical stacks. The gate electrode is positioned between source/drain regions and channel regions, creating a nested configuration that maximizes the use of vertical space and increases effective channel width within a compact footprint.
2Productivity
If minimum feature sizes are reduced to improve integration density, then integration density is improved, but device performance is degraded
Solution Approach 1:
The patent employs different semiconductor materials with varying properties in different regions of the vertical stack. Silicon germanium layers are used for source/drain regions while silicon layers form the channel regions, optimizing local electrical properties for each functional region and maintaining high device performance despite reduced feature sizes.
Solution Approach 2:
The patent utilizes composite material structures combining silicon and silicon germanium layers in vertical stacks. This composite approach allows optimization of different regions for specific functions (channel formation, source/drain contact, stress engineering) while maintaining overall device performance and enabling higher integration density.
3Length of moving object
If channel regions are modified to increase effective channel width, then effective channel width is improved, but manufacturing complexity is increased
Solution Approach 1:
The patent forms the complete vertical stack structure including alternating semiconductor layers and gate electrodes before final patterning steps. This preliminary formation of the 3D structure simplifies subsequent manufacturing steps compared to attempting to create the same effective channel width through complex planar patterning processes.
Solution Approach 2:
The patent replaces complex planar lithography and etching processes with vertical epitaxial growth methods to create the multi-layer stack structure. This substitution of manufacturing approaches simplifies the overall fabrication process by utilizing self-aligned vertical formation rather than multiple sequential planar patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the effective channel width of CFETs, allowing for better tuning of drive currents and improved device performance, addressing the challenges posed by reduced feature sizes.
Implementation Method 1
a first semiconductor layer is deposited over and contacting the first semiconductor nanostructure
Data Source
AI summary
A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.