CFET Channel Formation Using Sacrificial SiGe and Silicon Epitaxy
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in maintaining effective channel width and tuning device performance.
Innovation Solution
The formation of Complementary Field-Effect Transistors (CFETs) with modified channel regions, utilizing a multi-layer stack of semiconductor nanostructures and dummy SiGe layers, followed by selective etching and epitaxial growth of silicon to enhance channel width and replace dummy structures with replacement gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but maintaining effective channel width and device performance becomes difficult
Solution Approach 1:
The patent transitions from planar channel structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change allows the channel width to be controlled by the fin height and width rather than solely by gate length, enabling better control of effective channel width even as minimum feature sizes are reduced to increase integration density.
Solution Approach 2:
The patent introduces dummy SiGe layers with different germanium concentrations at specific locations within the FinFET structure. These dummy layers have locally modified properties (different etch rates, different stress characteristics) that allow selective modification of channel regions while maintaining the overall FinFET geometry, enabling precise control of local channel width and electrical characteristics.
2Manufacturing precision
If dummy SiGe layers are used to define channel regions, then channel width can be controlled, but additional etching and replacement processes are required
Solution Approach 1:
The dummy SiGe layers are deposited and patterned before the actual FinFET formation processes. These dummy structures serve as preliminary definitions of the channel regions, establishing the geometric boundaries early in the process sequence. This allows subsequent etching and replacement operations to proceed with well-defined targets, reducing the complexity of later steps.
Solution Approach 2:
The dummy SiGe layers act as intermediary structures that facilitate the formation of the final FinFET channel. They provide a temporary framework that guides the selective etching of sacrificial materials and the subsequent deposition of replacement gate stacks. The dummy layers are removed after serving their mediating function, leaving the desired channel geometry without requiring complex direct patterning steps.
3Manufacturing precision
If selective etching is used to remove dummy structures, then channel regions can be defined, but etching selectivity and control become critical
Solution Approach 1:
The patent creates local quality differences through the deposition of dummy SiGe layers with varying germanium concentrations at specific positions. These layers have different etch rates compared to the surrounding materials, creating naturally defined etching stop points and selectivity windows. This local differentiation simplifies the etching process by providing inherent guidance for selective material removal without requiring complex process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CFET structure achieves increased effective channel width and improved device performance tuning, enabling higher drive currents and efficient integration of semiconductor components.
Implementation Method 1
epitaxial growth of silicon to enhance channel width
Implementation Method 2
selective etching and epitaxial growth of silicon
Data Source
AI summary
A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.