CFET Common Metal Gate Structure Without Upper Gate Etch-Back
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges such as device damage and performance degradation due to the complex processing required for dual metal gate structures, particularly the upper gate etch-back process.
Innovation Solution
The method involves forming a common metal gate in a single step for complementary field-effect transistors (CFETs) using a silicon-containing passivation layer and a work function layer, eliminating the need for a thick n-type work function material and avoiding the upper gate etch-back process, which simplifies processing and enhances integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual metal gate structures with separate upper and lower gates are used, then threshold voltage tuning capability is improved, but device complexity and manufacturing difficulty increase due to the upper gate etch-back process
Solution Approach 1:
The patent merges the upper and lower gate structures into a single continuous gate that extends through the isolation structure. This unified gate structure eliminates the need for separate upper and lower gate fabrication processes, including the complex upper gate etch-back process, while maintaining the ability to tune threshold voltage through the gate's continuous presence around the channel region
Solution Approach 2:
The isolation structure serves as an intermediary element that the gate material continuously traverses. By forming the gate to extend through the isolation structure rather than requiring separate upper and lower gates, the patent simplifies the overall device structure while preserving threshold voltage control functionality
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but device damage and performance degradation occur due to complex processing
Solution Approach 1:
By combining the upper and lower gates into a single continuous structure that extends through the isolation structure, the patent reduces the number of fabrication steps and processing complexity. This simplification minimizes the risk of device damage during manufacturing while enabling continued scaling to higher integration densities
Solution Approach 2:
The patent extracts and eliminates the problematic upper gate etch-back process from the fabrication sequence. By designing the gate to be formed in a single continuous step through the isolation structure, the patent removes the source of device damage and performance degradation associated with the etch-back process, allowing reliable manufacturing at smaller feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity, avoids device damage, and increases integration density by eliminating the need for a thick n-type work function layer and simplifying the processing steps, while maintaining effective threshold voltage tuning for n-type transistors.
Implementation Method 1
forming a silicon-containing passivation layer around the work function material
Data Source
AI summary
A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.