Confined CFET S/D Contacts With Selective Inner Spacer Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing faces challenges in scaling transistors beyond single-digit nanometer nodes due to constraints in three-dimensional integration, particularly in forming wide backside power rails and incorporating backside signal wiring without increasing parasitic resistances and edge placement errors.
Innovation Solution
A method involving bonding wafers with alternating epitaxial layers to form stacked field-effect transistor devices, where backside power rails and signal wiring are integrated using a power delivery network with vias extending through bonding dielectric layers, allowing for wider power rails and reduced parasitic resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional integration is used to increase transistor density, then transistor density is improved, but parasitic resistances increase
Solution Approach 1:
The patent transitions from two-dimensional planar circuits to three-dimensional stacked circuits by bonding multiple semiconductor wafers together. Multiple tiers of transistors are formed on different wafer layers, enabling vertical stacking that increases transistor density while maintaining electrical performance through optimized via structures and bonding interfaces.
Solution Approach 2:
Bonding dielectric layers are introduced as intermediary materials between stacked semiconductor wafers. These dielectric layers provide electrical isolation and mechanical support, enabling the formation of wide backside power rails that reduce parasitic resistances while maintaining the three-dimensional integrated structure.
2Reliability
If wide backside power rails are formed to reduce parasitic resistances, then parasitic resistances are reduced, but manufacturing complexity increases
Solution Approach 1:
Power delivery networks and wide backside power rails are formed during the wafer bonding process itself, before final device assembly. This preliminary formation of power distribution structures simplifies subsequent manufacturing steps by establishing low-resistance electrical pathways early in the fabrication sequence.
Solution Approach 2:
The patent combines multiple functions into the bonding dielectric layer, which simultaneously provides electrical isolation between stacked wafers, mechanical support for wide power rails, and a substrate for forming backside power distribution networks. This merging of functions reduces the number of separate manufacturing steps required.
3Ease of manufacture
If conventional two-dimensional circuits are used, then manufacturing is simpler, but transistor density is limited
Solution Approach 1:
The patent extends conventional two-dimensional circuit fabrication into the third dimension by bonding multiple semiconductor wafers together. Each wafer contains tiers of transistors that are vertically stacked, multiplying the effective transistor density without requiring proportionally more complex manufacturing processes for each individual layer.
Solution Approach 2:
The semiconductor device is divided into multiple discrete wafer layers, each containing specific tiers of transistors and power delivery networks. This segmentation allows each layer to be fabricated and optimized independently before being bonded together, maintaining manufacturing simplicity while achieving high overall transistor density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased transistor density and reduced parasitic resistances, facilitating more efficient power delivery and signal transmission in three-dimensional semiconductor circuits.
Implementation Method 1
bonding a first wafer to a second wafer via a first bonding dielectric layer
Implementation Method 2
The second wafer includes a first stack of alternating layers of epitaxially grown semiconductor layers formed over a second bulk semiconductor material
Implementation Method 3
The second bulk semiconductor material is removed to uncover the first stack
Implementation Method 4
backside power rails in contact with vias that extend through the first bonding dielectric layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material. Fin structures are formed from the stack. The fin structures include channel structures formed of the first semiconductor material. The channel structures have opposing ends that are uncovered. Sidewall constraints are formed at the opposing ends of the channel structures. Each pair of the sidewall constraints laterally bounds a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region. S/D structures are formed on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints.