CFET Contact Integration With Vertical Interconnect Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CFET architectures face challenges in reducing device footprint and total interconnect metal length to minimize parasitic resistance, necessitating improvements in contact integration and metal routing.
Innovation Solution
A semiconductor structure with a bottom FET module and a top FET module stacked orthogonally, featuring a top-to-bottom interconnect and optimized metal routing through dual damascene integration, including trench/via structures and self-aligned contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar or FinFET architectures are used, then manufacturing is simpler, but device footprint and parasitic resistance are larger
Solution Approach 1:
The patent transitions from planar (2D) to three-dimensional (3D) stacked CFET architecture, stacking n-FET and p-FET vertically to reduce device footprint. This dimensional change enables higher integration density while managing contact integration complexity through self-aligned processes
Solution Approach 2:
The contact integration is segmented into multiple specialized layers: bottom liner for lateral coverage, top liner for vertical coverage, and dual damascene structures. This segmentation allows each layer to address specific integration challenges independently, managing overall complexity
2Length of stationary object
If interconnect metal length is reduced, then parasitic resistance decreases, but routing flexibility is constrained
Solution Approach 1:
Power distribution network is moved to the backside of the device, utilizing the vertical dimension and backside routing. This enables shorter interconnect paths while maintaining routing flexibility through the third dimension, reducing parasitic resistance without constraining design adaptability
Solution Approach 2:
The conventional front-side power distribution is inverted to back-side implementation. This inversion allows power delivery through the substrate, shortening metal paths and reducing parasitic resistance while preserving routing flexibility through alternative pathways
3Productivity
If dual damascene integration is implemented, then metal routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
Self-aligned contact holes and trenches are formed using preliminary patterning steps before metal deposition. This preliminary action ensures precise alignment of dual damascene structures, improving metal routing efficiency while reducing the need for complex alignment procedures during manufacturing
Solution Approach 2:
The structure utilizes self-aligned features where previously formed layers automatically define the position of subsequent layers. This self-service mechanism simplifies the manufacturing process by eliminating complex alignment steps, maintaining ease of manufacture while achieving high routing efficiency
Data Source
AI summary
A semiconductor structure includes a bottom field effect transistor (FET) module, the bottom FET module including a bottom metal gate, a pair of bottom source/drain (S/D) contacts, and a top FET module on the bottom FET module in a second direction that is orthogonal to the first direction, the top FET module including a top metal gate, a pair of top S/D contacts, and a top-to-bottom interconnect extending through the bottom FET module and the top FET module in the second direction, a bottom liner covering surfaces of the top-to-bottom interconnect along a plane parallel to the first direction and the second direction, and a top liner covering surfaces of the top-to-bottom interconnect along a plane orthogonal to the first direction.