CFET Front-to-Back Interconnect Using Deep Contact Plugs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced feature sizes, challenges arise in forming power and signal connections without violating design rules and requiring additional space, particularly in Complementary Field-Effect Transistors (CFETs).
Innovation Solution
The formation of deep contact plugs between gate-replacing structures in CFETs, which are integrated into the source/drain contact plug processes, allows for power and signal routing without cutting the gate-replacing structures, enabling smaller power tap cells and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional power and signal connection methods are used in CFETs, then design rules are violated and additional space is required, but integration density is reduced
Solution Approach 1:
The patent utilizes the vertical dimension by forming deep contact plugs that extend through multiple layers to connect front-side and back-side structures. This three-dimensional interconnection approach allows power and signal routing without requiring additional lateral space, thereby maintaining design rule compliance while reducing power tap cell area and improving integration density
2Ease of manufacture
If gate-replacing structures are cut for routing, then power and signal connections can be made, but gate structure integrity is compromised
Solution Approach 1:
The patent introduces deep contact plugs as intermediary structures that extend vertically through the device layers. These contact plugs provide the necessary routing capability for power and signal connections without requiring horizontal cuts through gate-replacing structures, thereby maintaining gate structure integrity while enabling manufacturable routing paths
3Ease of manufacture
If conventional interconnection structures are used, then fabrication is simpler, but resistance is higher and voltage drop increases
Solution Approach 1:
The patent employs deep contact plugs that extend vertically through multiple layers to create shorter and more direct electrical pathways. This three-dimensional interconnection approach reduces the lateral distance current must travel, thereby lowering resistance and voltage drop while maintaining compatibility with existing fabrication processes
Data Source
AI summary
A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug.