Semiconductor Layer Stack Dielectric Filling for CFET Isolation
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Solution Overview
Problem
Current semiconductor manufacturing processes for complementary FETs (CFETs) are inefficient, requiring numerous processing steps and often result in suboptimal electrical performance due to the complexity of forming dielectric isolation and spacers.
Innovation Solution
A method involving a layer stack with sacrificial layers of different semiconductor materials, protected by liner layers, is used to form a semiconductor structure. This method includes selective etching and chemical vapor deposition (CVD) to create dielectric material in cavities and recesses, reducing processing steps and ensuring flat, high-quality dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor manufacturing processes are used to form dielectric isolation and spacers for CFETs, then the devices can be fabricated, but the process requires numerous processing steps and results in suboptimal electrical performance
Solution Approach 1:
The patent applies preliminary action by forming recesses in the first sacrificial layers before removing the second sacrificial layers. This preparatory step enables subsequent dielectric material deposition to occur in pre-defined cavities, eliminating the need for separate cleaning steps and reducing overall process complexity while improving electrical performance through better dielectric layer quality
Solution Approach 2:
The patent uses liner layers as intermediary protective structures between the first and second sacrificial layers. These liner layers enable selective removal of the second sacrificial layers while protecting the first sacrificial layers, allowing dielectric material to be deposited in controlled cavities without requiring additional cleaning processes
2Productivity
If conventional etching and deposition processes are used, then dielectric material can be formed, but numerous cleaning steps are required and processing efficiency is reduced
Solution Approach 1:
The patent performs preliminary recess formation in the first sacrificial layers before dielectric deposition. This advance preparation creates defined cavities that guide dielectric material deposition directly into the intended regions, eliminating the need for subsequent cleaning steps to remove excess material and significantly improving processing efficiency
Solution Approach 2:
The selective etching process inherently defines the deposition regions through the presence or absence of sacrificial layers. The structure itself guides where dielectric material should be deposited, making the process self-directed and eliminating the need for separate cleaning operations to correct misplaced material
3Manufacturing precision
If dielectric material is deposited without pre-formed cavities, then the process is simpler, but cleaning steps are required and dielectric layer quality is compromised
Solution Approach 1:
The patent forms recesses in the first sacrificial layers as a preliminary step before dielectric deposition. This advance cavity formation ensures that dielectric material is deposited only in the intended regions with precise control over thickness and uniformity, achieving high manufacturing precision while the integrated nature of the process steps keeps overall complexity manageable
Solution Approach 2:
The liner layers serve as intermediary structures that protect the first sacrificial layers during selective etching of the second sacrificial layers. This mediation creates well-defined cavities that guide dielectric deposition, ensuring high dielectric layer quality through controlled filling without requiring additional complex process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the manufacturing process, reduces the need for cleaning steps, and enhances electrical performance by providing stable, high-quality dielectric isolation and spacers, facilitating further device scaling and improved CFET fabrication.
Implementation Method 1
reacting, as a film-forming gas, an oxygen-containing silicon compound gas with a non-oxidizing hydrogen-containing gas in a state in which at least the non-oxidizing hydrogen-containing gas is plasmarized, to form a film of a flowable silanol compound
Implementation Method 2
in a state in which at least the non-oxidizing hydrogen-containing gas is plasmarized
Implementation Method 3
subsequently, annealing the film of flowable silanol compound into the first dielectric material
Implementation Method 4
forming recesses in the first sacrificial layers of the layer stack by laterally etching back the end surfaces of the first sacrificial layers from opposite ends of the layer stack, by selective etching; removing the at least one second sacrificial layer of the second sub-stack by selective etching
Data Source
Figure 1aa~1bb
Figure 1a~1c
Figure 2a~3b
AI summary
The present invention provides a method for forming a semiconductor structure (100), the method comprising: forming a layer stack (110; 210) on a substrate (102; 202), the layer stack comprising: a first sub-stack, a second sub-stack (130; 230) on the first sub and comprising a plurality of sacrificial layers alternating between first and second sacrificial layers (132a; 232a, 132b), a third sub-stack (140; 240) on the second sub-stack, forming recesses (160; 260) in the first sacrificial layers, removing the at least one second sacrificial layer, depositing dielectric material in the at least one cavity; and depositing dielectric material in the recesses of the first sacrificial layers; wherein at least one of said acts of depositing dielectric material in the at least one cavity; and depositing dielectric material in the recesses of the first sacrificial layers, is performed by a first chemical vapor deposition method, CVD method.