CFET Differential Pair Layout for High-Density Low-Variation Circuits
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high device density and reduced fabrication variability due to lithographic and performance variance, particularly in three-dimensional circuit components.
Innovation Solution
The use of complementary field effect transistors (CFETs) with vertically stacked transistors of complementary types, such as p-type and n-type, to enhance density and reduce discrimination errors through symmetrical current control and process variation correlation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional circuit components are used to increase device density, then device density is improved, but fabrication variability and lithographic challenges worsen
Solution Approach 1:
The patent transitions from planar two-dimensional circuit layouts to three-dimensional vertically stacked transistor configurations. By stacking n-type and p-type transistors vertically, the device achieves higher density without proportionally increasing lithographic complexity, as the vertical stacking is achieved through sequential deposition and patterning steps rather than requiring higher-resolution lithography.
Solution Approach 2:
The patent divides the circuit into complementary n-type and p-type transistor pairs that are vertically stacked and laterally separated. This segmentation allows each transistor type to be independently optimized and fabricated, reducing the propagation of fabrication variability across the entire circuit while maintaining high density through the compact vertical arrangement.
2Quantity of substance
If vertically stacked transistors are used, then circuit density is improved, but discrimination errors from process variation worsen
Solution Approach 1:
The patent employs asymmetric lateral positioning of complementary n-type and p-type transistors within the vertical stack, where each transistor type is offset from the other. This asymmetric arrangement, combined with common-centroid layout techniques, ensures that process variations affect both transistors equally, causing errors to cancel out and reducing discrimination errors in differential circuits.
Solution Approach 2:
The patent implements common-centroid matching and symmetrical current control mechanisms that provide inherent feedback compensation for process variations. By arranging transistor pairs with matched geometries and positions, the circuit automatically compensates for fabrication variations, reducing discrimination errors without requiring additional correction circuits.
3Measurement precision
If complementary transistor pairs are used with symmetrical current control, then signal-to-noise ratio is improved, but device complexity increases
Solution Approach 1:
The patent merges the n-type and p-type transistors into integrated vertically stacked complementary field-effect transistor (CFET) structures. This merging allows both transistor types to share common fabrication processes, interconnect structures, and substrate regions, achieving symmetrical current control and improved signal-to-noise ratio while minimizing the increase in device complexity through shared infrastructure.
Data Source
AI summary
Semiconductor devices using complementary field effect transistors are provided. A semiconductor device includes a first complementary field effect transistor (CFET) pair. The first CFET pair includes a first n-type transistor having a first gate electrode coupled with a first input of a differential pair. The first CFET pair includes a first p-type transistor having a second gate electrode coupled with the first input of the differential pair. The semiconductor device includes second CFET pair. The second CFET pair includes a second n-type transistor having a third gate electrode coupled with a second input of the differential pair. The second CFET pair includes a second p-type transistor having a fourth gate electrode coupled with the first input of the differential pair.