CFET Source/Drain Doping With Upper-Layer Recrystallization Control

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Solution Overview

Problem

As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining device performance and manufacturing ease due to thermal-induced relaxation of source/drain regions.

Innovation Solution

The formation of complementary field-effect transistors (CFETs) with a lower nanostructure-FET and an upper nanostructure-FET, where the upper source/drain region is formed by implanting dopants that amorphize a portion, followed by a rapid thermal process to recrystallize and activate the dopants, while keeping the lower source/drain region below a relaxation temperature.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a rapid thermal process is used to activate dopants in the upper source/drain region, then device performance is improved through dopant activation, but thermally-induced relaxation of the lower source/drain region occurs

Engineering Contradiction:
Improvedevice performanceVSAvoidlower source/drain region stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies different thermal treatments to different regions: the upper source/drain region undergoes rapid thermal processing for dopant activation, while the lower source/drain region is maintained below relaxation temperature. This spatial differentiation of thermal quality allows dopant activation where needed without causing relaxation in regions where it would be harmful.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The CFET structure is segmented into upper and lower nanostructure-FETs with independent source/drain regions. This segmentation allows independent thermal processing of each region's source/drain, enabling the upper region to receive high-temperature treatment while the lower region remains protected from relaxation effects.

Inventive Principle:
Principle #1Segmentation

2Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but thermal management and manufacturing precision become more difficult

Engineering Contradiction:
Improveintegration densityVSAvoidsource/drain region control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from planar transistor integration to three-dimensional vertically-stacked CFET architecture. By stacking upper and lower nanostructure-FETs vertically, integration density is dramatically increased without further reducing lateral feature sizes, thereby avoiding the manufacturing precision and thermal management challenges associated with miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The device is segmented into independently processable upper and lower source/drain regions, allowing separate thermal treatment and dopant activation. This segmentation enables precise control over each region's properties even in the compact stacked geometry, maintaining manufacturing precision despite high integration density.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves device performance by activating dopants in the upper source/drain region without causing thermally-induced relaxation of the lower source/drain region, thereby enhancing both performance and manufacturing ease of the completed CFETs.

Implementation Method 1

followed by a rapid thermal process to recrystallize and activate the dopants

Methodology Applied
Scientific EffectRapid thermal process: Heating

Implementation Method 2

implanting dopants that amorphize a portion

Methodology Applied
Scientific EffectAmorphization: Phase Change

Data Source

PatentUS20250056852A1Source/drain regions in complementary field effect transistors and methods of forming the same
Publication Date: 2025.02.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250056852A1 patent drawing
  • US20250056852A1 patent drawing
  • US20250056852A1 patent drawing

AI summary

A method includes forming first nanostructures over a substrate, then forming second nanostructures over the plurality of first nanostructures. A first source/drain region is epitaxially grown adjacent the first nanostructures, and a second source/drain region is epitaxially grown over the first source/drain region and adjacent the second nanostructures. An implantation process is performed to implant impurities into the second source/drain region, wherein the implantation process forms an amorphous region within the second source/drain region. At least one rapid thermal process is performed on the second source/drain region, wherein performing each rapid thermal process recrystallizes a portion of the amorphous region.