CFET Resistance Measurement Structure for Drain Contact Extraction
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Solution Overview
Problem
Integrated circuit devices with stacked transistors face challenges in accurately measuring resistances of conductive elements, which affects their performance and area efficiency.
Innovation Solution
The proposed solution involves a resistance measuring structure comprising two CFET stacks and conductive connections that electrically connect drain regions of transistors, allowing for the calculation of upper and lower drain contact resistances using voltage and current measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional resistance measurement methods are used in stacked transistor devices, then measurement simplicity is maintained, but measurement precision deteriorates due to inability to accurately isolate and measure individual conductive element resistances
Solution Approach 1:
The measurement structure is segmented into multiple independent measurement paths, each dedicated to measuring specific conductive elements (e.g., upper drain contact resistance, lower drain contact resistance, interconnect resistance). By dividing the measurement function into separate segments, each path can accurately measure its target parameter without interference from other elements, thus improving measurement precision while maintaining manageable complexity through modular design
Solution Approach 2:
Dummy transistor structures are introduced as intermediary elements to facilitate resistance measurement. These dummy transistors serve as mediators that allow measurement current to flow through specific conductive paths while providing controlled electrical characteristics. The intermediary structures enable isolation of individual resistance components for accurate measurement without requiring complex probe configurations
2Area of stationary object
If stacked transistor structures are implemented to reduce area, then area efficiency is improved, but measurement difficulty increases due to limited access to internal conductive elements
Solution Approach 1:
The measurement approach transitions from planar two-dimensional probing to three-dimensional access by utilizing vertical interconnect structures (through-silicon vias, conductive pillars) that extend through multiple stacking layers. This dimensional transition enables measurement probes to access internal conductive elements (such as drain contacts and interconnects) that would be inaccessible in conventional planar devices, thus enabling resistance measurement in compact stacked architectures without increasing device area
Solution Approach 2:
Dummy transistor structures are created as copies of the actual transistor stack, replicated specifically for measurement purposes. These copy structures contain identical conductive elements and interconnects but are configured to provide measurement access points. By copying the essential measurement-relevant features of the stacked transistors into dedicated measurement structures, the patent enables accurate resistance measurement while maintaining the compact area-efficient design of the functional stacked devices
Data Source
AI summary
Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.