CFET Layout with Dummy Transistors for Reduced Footprint
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Solution Overview
Problem
Current designs of vertically stacked complementary field-effect transistors (CFETs) are not fully satisfactory in terms of efficient utilization of chip area, leading to unused space due to the fixed number and arrangement of dielectric structures and inactive transistors.
Innovation Solution
The proposed solution involves rearranging the layout of transistors by incorporating dummy transistors in unused areas and optimizing routing to reduce the number of dielectric structures, thereby reducing the overall footprint of the device without affecting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fixed number and arrangement of dielectric structures and inactive transistors are maintained in current CFET designs, then the structural simplicity is preserved, but the chip area utilization efficiency deteriorates due to unused space
Solution Approach 1:
The patent merges previously separate elements (active transistors, dummy transistors, and dielectric structures) into a unified layout where dummy transistors are strategically placed in unused areas to fill gaps. This combining approach eliminates wasted space while maintaining functional integrity, directly improving chip area utilization without proportionally increasing complexity
Solution Approach 2:
The patent utilizes the vertical stacking dimension to arrange transistors in multiple layers (first and second semiconductor layers), allowing efficient use of three-dimensional space. By transitioning from a two-dimensional planar layout to a three-dimensional vertically-stacked configuration, the design maximizes chip area utilization while keeping the footprint compact
2Area of stationary object
If the number of dielectric structures is reduced to minimize unused space, then the chip area efficiency is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary placement of dummy transistors in unused areas during the layout design phase, before final fabrication. This advance planning ensures that the reduced number of dielectric structures are optimally positioned to minimize footprint while maintaining alignment with existing structures, thereby managing manufacturing precision requirements through careful pre-positioning
Solution Approach 2:
The patent applies different layout strategies to different regions of the chip: functional areas use standard designs while unused areas are specifically optimized with dummy transistors and reduced dielectric structures. This localized optimization allows footprint reduction in non-critical areas without compromising the precision requirements of functional regions
Data Source
AI summary
A semiconductor device includes a first semiconductor layer and a second semiconductor layer stacked vertically over a substrate. The first semiconductor layer and the second semiconductor layer extend laterally across the substrate. The semiconductor device includes a first gate structure and a second gate structure extending vertically from the substrate and perpendicular to the first semiconductor layer and the second semiconductor layer. The first gate structure engages the first semiconductor layer and the second semiconductor layer to form a first transistor and a second transistor, respectively. The second gate structure engages the first semiconductor layer and the second semiconductor layer to form a third transistor and a fourth transistor, respectively. The first gate structure is laterally adjacent to the second gate structure. The third transistor is an inactive transistor. The second transistor and the fourth transistor are active transistors.