CFET Local Interconnect Layout for Embedded Power Taps
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in reducing the size of power tap areas and optimizing routing resources due to the inclusion of independent power tap cells and disconnected gate connections in CFET devices.
Innovation Solution
Incorporating power tap structures as local interconnects within functional cells, particularly using CFET devices, which allows for embedded power tap cells without disrupting gate connections, thereby reducing the power tap area and maximizing routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent power tap cells are included in CFET devices, then power delivery is achieved, but power tap area increases and routing resources are reduced
Solution Approach 1:
The patent merges the power tap cell with the functional cell by integrating power tap structures as local interconnects within the functional cell layout. This consolidation eliminates the need for separate independent power tap cells, thereby reducing the overall power tap area while maintaining reliable power delivery to the CFET devices.
Solution Approach 2:
The functional cell is designed to serve multiple functions simultaneously: it performs its primary computational function while also housing power tap structures that deliver power to adjacent CFET devices. This multi-functionality reduces the dedicated area required for power delivery infrastructure.
2Reliability
If independent power tap cells are included in CFET devices, then power delivery is achieved, but routing resources are reduced
Solution Approach 1:
By combining power tap structures with functional cell interconnects, the patent reduces the number of separate routing paths required. Power delivery routes are integrated into the existing signal routing infrastructure, thereby conserving routing resources and reducing overall device complexity.
3Area of stationary object
If power tap cells are integrated within functional cells, then power tap area is reduced, but gate connections may be disrupted
Solution Approach 1:
The patent applies local quality by carefully positioning power tap structures within specific regions of the functional cell that do not interfere with gate connections. The power tap cell is integrated into the functional cell layout in a manner that preserves the electrical connectivity and operational integrity of the gate terminals.
Solution Approach 2:
The functional cell is segmented into distinct functional zones: areas for power tap structures, areas for gate connections, and areas for signal routing. This spatial segmentation allows power delivery infrastructure to be incorporated without disrupting gate connection pathways.
Data Source
AI summary
An integrated circuit (IC) device includes a complementary field-effect transistor (CFET) device, a first conductor at a first side of the CFET device, and a second conductor at a second side of the CFET device. The second side is opposite the first side along a thickness direction of the CFET device. The CFET device includes a local interconnect electrically coupling the first conductor to the second conductor, and a gate arranged in a plane that intersects the local interconnect. The gate is electrically isolated from the local interconnect.