CFET Epitaxial Isolation Structure for Source-Drain Leakage
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing current leakage in integrated circuit (IC) structures, particularly in the source/drain epitaxial structures of complementary FET (CFET) devices.
Innovation Solution
The implementation of an epitaxial stack as an isolation structure between the source/drain epitaxial structures of CFET devices, which includes alternating layers of different compositions to enhance etch selectivity and reduce current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional isolation structures are used between source/drain epitaxial structures, then manufacturing is simpler, but current leakage increases
Solution Approach 1:
The isolation structure employs a composite epitaxial stack comprising alternating layers of first and second epitaxial materials with different compositions and conductivities. This composite structure provides superior electrical isolation performance compared to conventional single-material isolation structures, effectively reducing current leakage between source/drain regions while maintaining manufacturability through established epitaxial growth processes.
Solution Approach 2:
The isolation structure is segmented into multiple thin epitaxial layers rather than using a single thick layer. This segmentation into alternating high-conductivity and low-conductivity layers creates a more effective barrier against current leakage while allowing each layer to be grown with controlled thickness and composition, optimizing both isolation performance and manufacturing feasibility.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases, but current leakage worsens
Solution Approach 1:
The epitaxial growth parameters (temperature, pressure, gas flow rates, precursor ratios) are precisely controlled and optimized to achieve the desired layer thicknesses, compositions, and conductivity profiles. By adjusting these parameters, the isolation structure is tailored to provide adequate electrical isolation even as device dimensions are scaled down, thereby maintaining low current leakage while benefiting from increased functional density and production efficiency.
3Reliability
If alternating layers of different compositions are used in the epitaxial stack, then etch selectivity and electrical isolation improve, but manufacturing precision requirements increase
Solution Approach 1:
Different regions of the epitaxial stack are engineered with locally optimized properties. The first and second epitaxial materials are selected and configured to provide specific local characteristics: one material provides etch selectivity for selective removal processes, while the other provides low conductivity for electrical isolation. This local quality differentiation achieves superior electrical isolation and etch selectivity while managing manufacturing precision through targeted material properties rather than uniform composition control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces current leakage by creating a robust epitaxial isolation structure that improves the electrical isolation between the source/drain epitaxial structures, thereby enhancing the overall performance and reliability of the semiconductor devices.
Implementation Method 1
an epitaxial stack as an isolation structure between the source/drain epitaxial structures of CFET devices
Data Source
AI summary
A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.