CFET Interconnect Layout Using Epitaxial Silicon Conduction Paths
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Solution Overview
Problem
Providing efficient interconnects in Complementary Field-Effect Transistor (CFET) devices is challenging due to space constraints and additional process complexities, particularly in connecting the source, drain, and gate of transistors, which often require front side and back side metal layers, leading to increased capacitance and power consumption.
Innovation Solution
Implementing lateral conductive paths within and between CFET devices using doped epitaxial silicon, which reduces the need for front side and back side metal layer connections, and optimizing the placement of through-silicon vias (TSVs) to minimize parasitic capacitance and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If front side and back side metal layers are used to connect source, drain, and gate of transistors, then connectivity is achieved, but capacitance and power consumption increase
Solution Approach 1:
The patent extracts the interconnect function from the metal layer system and relocates it to the epitaxial silicon substrate. By forming conductive paths directly in the substrate using doping processes, the need for extensive front-side and back-side metal layer connections is reduced, thereby decreasing parasitic capacitance and power consumption while maintaining connectivity.
Solution Approach 2:
The patent introduces epitaxial silicon as an intermediary material that provides conductive paths between transistor terminals. This intermediary substrate-based conduction path replaces direct metal layer connections, reducing the capacitive coupling between adjacent metal interconnects and lowering overall power consumption.
2Reliability
If front side and back side metal layers are used for transistor connections, then interconnect functionality is provided, but device area increases
Solution Approach 1:
The patent merges the interconnect function with the substrate structure itself. By integrating conductive paths directly into the epitaxial silicon substrate rather than relying on separate metal layer systems, the overall device footprint is reduced as interconnect routing is accomplished within the existing substrate volume rather than requiring additional lateral metal layer space.
3Adaptability or versatility
If multiple metal layers are used for interconnects, then routing flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent replaces the mechanical/metal-based interconnect system with a semiconductor-based conduction system. Instead of using multiple deposited and patterned metal layers, the invention uses doping processes to create conductive regions directly in the epitaxial silicon substrate, simplifying the manufacturing process while maintaining routing capability through substrate-based conduction paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, minimizes area usage, and enhances performance by eliminating connections to metal layers, thereby decreasing coupling capacitance and optimizing routing resources.
Implementation Method 1
Implementing lateral conductive paths within and between CFET devices using doped epitaxial silicon
Implementation Method 2
doped epitaxial silicon
Implementation Method 3
optimizing the placement of through-silicon vias (TSVs) to minimize parasitic capacitance
Data Source
AI summary
Embodiments herein relate to interconnects in Complementary Field-Effect Transistor (CFET) devices. In one aspect, an epitaxial silicon material is used to provide a conductive path which extends laterally between first and second CFET devices. In one example, the conductive path extends between drains of n-channel and p-channel Field-Effect Transistors (FETs) of the CFETs. In another example, the conductive path extends between gates of the n-channel and p-channel FETs of the CFETs. Each CFET may be provided in area allocated to a standard cell. In another aspect, an area of a standard cell allocated to passive devices is used for a through-silicon via which extends from a front side metal layer to a back side metal layer.