CFET Fin Structure Using Double SOI for Higher Density
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Solution Overview
Problem
Conventional CFET device fabrication is limited by the height/width ratio of fins, which restricts the density of transistors per unit area while maintaining acceptable electrical performance.
Innovation Solution
A process involving a double semiconductor-on-insulator substrate is developed, where two single-crystal semiconductor layers and electrically insulating layers are transferred onto a carrier substrate, allowing precise control of channel height and separation, and optimizing materials and doping for enhanced carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of the fins is decreased to increase transistor density, then the density of transistors per unit area is improved, but the electrical performance deteriorates due to insufficient current capacity
Solution Approach 1:
The patent transitions from planar fins to three-dimensional stacked fins, adding a vertical dimension to the transistor structure. This allows multiple transistor channels to be stacked vertically within the same footprint, increasing transistor density without reducing fin width and thereby maintaining electrical performance.
Solution Approach 2:
The patent implements nested structures where multiple FinFET transistors are stacked vertically, with each fin containing a channel. The stacked configuration allows one transistor structure to be nested within the vertical space of another, increasing density while preserving the electrical characteristics of each individual fin.
2Reliability
If the height of the active zones is increased to maintain current capacity, then the electrical performance is improved, but the manufacturing precision deteriorates due to technological limitations in fin fabrication
Solution Approach 1:
By stacking fins vertically, the patent achieves increased effective channel height without requiring individual fins to have excessive height. The vertical stacking distributes the height requirement across multiple manageable fins, each within manufacturable dimensions, while collectively providing the necessary current capacity.
3Ease of manufacture
If conventional bulk silicon substrate with sacrificial layer is used, then the fabrication process is simplified, but the transistor density is limited by fin height/width ratio constraints
Solution Approach 1:
The patent adopts stacked FinFET architecture that utilizes vertical space to increase transistor density. Multiple channels are stacked vertically within the same footprint, achieving higher density without complicating the fundamental fabrication process of defining fins and channels in the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased transistor density with improved electrical performance by precisely controlling channel height and using materials like strained silicon and silicon-germanium, while minimizing thermal damage and maintaining low roughness.
Implementation Method 1
a first layer-transfer step in order to transfer the first electrically insulating layer and the first single-crystal semiconductor layer to the carrier substrate, forming a first semiconductor-on-insulator substrate, the first layer-transfer step comprising a heat treatment at a sufficiently high temperature to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS
Data Source
AI summary
A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.