Double Cross-Coupled CFET Flip-Flop Layout for Routing Congestion

The patent transitions from traditional 2D planar circuit layout to 3D vertical stacking architecture. Multiple transistor layers are stacked vertically above each other on the substrate, with interconnect structures extending through multiple layers. This dimensional change allows significantly higher transistor density while managing wiring complexity through vertical interconnect access points that reduce the need for extensive lateral routing.

The patent implements nested interconnect structures where conductive pathways are embedded within and between transistor layers. Interconnect structures are positioned at multiple vertical levels, with lower-level interconnects nested within regions occupied by upper-level transistors and vice versa. This nesting approach allows efficient three-dimensional routing that minimizes wiring congestion by utilizing vertical space for signal distribution.

The patent utilizes vertical dimension for interconnect routing, with conductive structures extending through multiple transistor layers. This three-dimensional interconnect approach provides multiple routing paths through the vertical stack, ensuring robust connectivity without requiring proportional increases in lateral metal track area. Signals can be routed vertically between layers, reducing the need for extensive planar metal distribution networks.

The interconnect structures serve multiple functions simultaneously: they provide electrical connectivity between stacked transistor layers, act as shielding structures, and function as part of the power distribution network. This multi-functionality reduces the need for separate dedicated structures for each function, thereby maintaining comprehensive connectivity while minimizing the total device area occupied by interconnect infrastructure.