CFET N-Type GAAFET Fabrication Without a Sacrificial Layer
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Solution Overview
Problem
The integration of a middle dielectric layer between n-type and p-type GAAFETs in complementary field-effect transistor (CFET) devices poses challenges, particularly in forming a sacrificial layer that does not impact the channel regions of the transistors, and existing methods are complex and inefficient.
Innovation Solution
The use of high-performance thin-film transistor (HPTFT) materials, specifically non-crystalline silicon, for the source, drain, and channel regions of the n-type GAAFET, which are deposited and patterned instead of being grown epitaxially, simplifying the process and eliminating the need for a sacrificial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a sacrificial layer is formed on the p-type GAAFET for epitaxial growth of n-type regions, then the n-type source, drain, and channel regions can be grown, but the sacrificial layer formation and subsequent removal process increases device complexity and processing steps
Solution Approach 1:
The patent extracts and eliminates the sacrificial layer from the process by using deposited non-crystalline silicon that does not require a sacrificial layer for formation. The n-type source, drain, and channel regions are directly deposited on the p-type GAAFET without needing a sacrificial layer, thereby removing the complexity of sacrificial layer formation, epitaxial growth, and subsequent removal steps.
Solution Approach 2:
The patent changes the material state and deposition method parameter from epitaxial growth (which requires a sacrificial layer) to physical vapor deposition of non-crystalline silicon. This parameter change allows direct deposition of n-type regions without the need for a sacrificial layer, simplifying the overall process.
2Manufacturing precision
If epitaxial growth is used to form n-type source, drain, and channel regions, then the regions can be grown with proper crystal structure, but the process requires a sacrificial layer and multiple processing steps
Solution Approach 1:
The patent removes the sacrificial layer requirement by using deposition instead of epitaxial growth. The non-crystalline silicon can be directly deposited to form n-type source, drain, and channel regions without needing a sacrificial layer, thereby reducing the number of processing steps while maintaining manufacturing precision through controlled deposition parameters.
Solution Approach 2:
The patent uses deposition to create a copy of the desired n-type region structure directly on the p-type GAAFET without needing the intermediate sacrificial layer template. This allows direct formation of the final structure in fewer steps.
3Ease of manufacture
If a sacrificial layer is removed via etching and backfilled with dielectric material, then the middle dielectric layer is formed, but this process increases manufacturing complexity and processing time
Solution Approach 1:
The patent extracts and eliminates the sacrificial layer entirely from the process. By using deposited non-crystalline silicon that does not require a sacrificial layer, the patent removes the time-consuming steps of sacrificial layer etching and dielectric backfilling, significantly reducing processing time while maintaining ease of manufacture through direct deposition methods.
4Manufacturing precision
If the sacrificial layer is used as a seed layer for epitaxial growth, then the n-type regions can be grown, but the subsequent removal of the sacrificial layer risks impacting the channel regions
Solution Approach 1:
The patent extracts and eliminates the sacrificial layer from the process, using direct deposition of non-crystalline silicon instead. This removes the source of potential damage to channel regions during sacrificial layer removal while maintaining manufacturing precision through controlled deposition parameters that ensure proper n-type region formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation of the middle dielectric layer, reduces processing complexity, and ensures that the channel regions of both n-type and p-type GAAFETs are not affected during the formation of the middle dielectric layer, enhancing the overall efficiency and reliability of the CFET device.
Implementation Method 1
individual of the first layers comprising non-crystalline silicon... individual of the second layers comprising non-crystalline silicon
Data Source
AI summary
N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.