CFET Dielectric Gap-Fill for High-Aspect-Ratio S/D Isolation
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Solution Overview
Problem
The fabrication of complementary field effect transistor (CFET) devices faces challenges in isolating vertically stacked GAA devices due to high aspect ratios, which exceed conventional fabrication processes' tolerance limits, particularly during source/drain epitaxy, affecting device performance and consistency.
Innovation Solution
A method involving the deposition of dummy fills and spacers in source/drain canyons, followed by precise etching to create uniform voids, and filling these voids with insulators, ensuring consistent isolation and reduced process tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for device isolation, then the process is simpler, but the manufacturing precision deteriorates due to high aspect ratio exceeding tolerance limits
Solution Approach 1:
The patent applies preliminary action by depositing dummy fill material into the S/D canyon before the actual isolation process. This dummy fill serves as a placeholder that defines the target depth height, enabling subsequent precise etching and isolator deposition. The preliminary placement of dummy fill allows the process to achieve high manufacturing precision in device isolation by establishing a reference structure before the critical isolation steps.
2Manufacturing precision
If the number of fabrication steps is reduced, then productivity improves, but manufacturing precision deteriorates due to fewer isolation checkpoints
Solution Approach 1:
The patent merges multiple functions into the dummy fill structure: it serves as a depth reference, an etch stop layer, and a template for isolator deposition. By combining these functions into a single structural element, the process achieves uniform insulator deposition (high manufacturing precision) while reducing the number of separate fabrication steps (improved productivity). The dummy fill integrates multiple control functions that would otherwise require separate process steps.
3Reliability
If high aspect ratio structures are used for CFET stacking, then device performance improves, but manufacturing precision deteriorates due to process tolerance limits
Solution Approach 1:
The patent introduces dummy fill as an intermediary structure that mediates between the high aspect ratio CFET stacking requirement and the manufacturing precision constraint. The dummy fill material with its specific etch selectivity acts as a mediator that enables precise depth control during etching, allowing the high aspect ratio structure to be fabricated with the necessary precision. This intermediary element bridges the gap between the conflicting requirements of high device performance and strict process tolerance compliance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision and consistency of device isolation, improving the manufacturing process for CFET devices by reducing step count and ensuring uniformity in insulator deposition, thereby enhancing device performance.
Implementation Method 1
depositing a dummy fill based on a target depth height into the S/D canyon
Implementation Method 2
depositing a dummy fill based on a target depth height into the S/D canyon
Implementation Method 3
depositing a spacer cover on the sidewall of the first GAA CFET, and on the sidewall of the second GAA CFET
Implementation Method 4
etching away the dummy fill to create a void in the S/D canyon
Implementation Method 5
etching away the dummy fill to create a void in the S/D canyon
Implementation Method 6
depositing an isolator in the void at the target depth height
Implementation Method 7
depositing an isolator in the void at the target depth height
Data Source
AI summary
A system and method for fabricating a plurality of gate all around (GAA) complementary field effect transistors (CFETs). The fabrication method includes: fabricating a plurality of adjacent epitaxy layers, each of the plurality of epitaxy layers separated by a source/drain (S/D) canyon, each canyon defined by a sidewall of a first GAA CFET, and a sidewall of a second GAA CFET; depositing a dummy fill based on a target depth height into the S/D canyon; depositing a spacer cover on the sidewall of the first GAA CFET, and on the sidewall of the second GAA CFET; etching away the dummy fill to create a void in the S/D canyon; and depositing an isolator in the void at the target depth height.