CFET Gate Electrode Conductive Structure Routing

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Solution Overview

Problem

Integrated circuits (ICs) with complementary field-effect transistor (CFET) devices face challenges in routing resources and flexibility due to the lack of an isolated conductive structure across the gate electrode, necessitating additional metal layers for electrical connections.

Innovation Solution

Incorporating a conductive structure across an isolation layer within the gate electrode of CFET devices, allowing source/drain structures of the upper FET to be electrically connected without using a segment of an overlying metal layer, thereby reducing routing resource requirements and enhancing flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional CFET device structure without isolated conductive structure is used, then device structure is simpler, but routing flexibility and resource efficiency deteriorate due to lack of isolated conductive structure across gate electrode

Engineering Contradiction:
Improverouting flexibilityVSAvoiddevice structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The gate electrode region is segmented into multiple parts: the main gate electrode, an isolation layer, and a conductive structure. This segmentation creates distinct functional zones that enable independent electrical connections, allowing source/drain structures to be connected without relying on overlying metal layers, thus improving routing flexibility while maintaining manageable device complexity through organized structural division

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces a new dimensional element by placing a conductive structure in a different spatial dimension (within the gate electrode region, across the isolation layer) rather than relying solely on planar metal layers above the device. This dimensional change provides additional routing pathways and connection options, enhancing adaptability without proportionally increasing overall device complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If additional metal layers are used for electrical connections in CFET devices, then routing connections are achieved, but routing resource requirements and device complexity increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidmetal layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive structure within the gate electrode region serves multiple functions: it provides electrical connection between source/drain structures, acts as part of the gate electrode assembly, and enables routing without requiring additional dedicated metal layers. This multi-functionality achieves reliable electrical connections while avoiding the need for extra metal layers, thus reducing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The gate electrode region itself is designed to provide the electrical connection function that would otherwise require separate metal layers. The conductive structure integrated within the gate electrode assembly performs the connection task internally, making the gate electrode structure self-sufficient for both its primary control function and the additional routing function, thereby eliminating the need for additional metal layers

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240370628A1IC device
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240370628A1 patent drawing
  • US20240370628A1 patent drawing
  • US20240370628A1 patent drawing

AI summary

An IC device includes a gate electrode extending along a first direction, a channel extending through the gate electrode in a second direction perpendicular to the first direction and positioned at a first elevation along a third direction perpendicular to each to the first and second directions, an isolation layer positioned within the gate electrode at a second elevation different from the first elevation, first and second source/drain (S/D) structures adjacent to the channel and positioned on opposite sides of the gate electrode at the first elevation, third and fourth S/D structures positioned on opposite sides of the gate electrode at the second elevation, and a conductive structure extending in the second direction and electrically connected to each of the third and fourth S/D structures.