CFET Gate Electrode Conductive Structure Routing
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Solution Overview
Problem
Integrated circuits (ICs) with complementary field-effect transistors (CFETs) face challenges in routing resources and flexibility due to the lack of an isolated conductive structure across the gate electrode, requiring additional metal layers for electrical connections.
Innovation Solution
Incorporating a conductive structure over an isolation layer within the gate electrode of CFET devices, allowing source/drain structures of the upper FET to be electrically connected without using a segment of the overlying metal layer, thereby reducing routing resource requirements and enhancing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional metal layers are used to create isolated conductive structures across gate electrodes in CFET devices, then routing flexibility and electrical connection capability are improved, but device complexity and manufacturing process steps increase
Solution Approach 1:
The patent utilizes the vertical dimension by forming the conductive structure within the gate electrode thickness rather than adding horizontal metal layers. The gate electrode extends from the first semiconductor region through the second semiconductor region, and the conductive structure is embedded within this vertical gate structure, enabling isolated electrical connections without increasing lateral routing layers.
Solution Approach 2:
The conductive structure is nested within the gate electrode, which itself is nested between the first and second semiconductor regions. This nested configuration allows the conductive structure to be embedded inside the gate electrode volume, providing isolated electrical connections while maintaining a compact vertical stack architecture typical of CFET devices.
2Reliability
If additional metal layers are used to create isolated conductive structures, then electrical connection capability between adjacent circuit elements is improved, but manufacturing precision requirements and process steps increase
Solution Approach 1:
The conductive structure is formed within the gate electrode during the gate electrode formation process itself, before subsequent interconnect layers are deposited. This preliminary formation of the isolated conductive structure within the gate electrode eliminates the need for additional alignment and patterning steps that would be required if separate metal layers were used, thereby reducing manufacturing precision requirements.
3Device complexity
If conventional CFET structures without isolated conductive structures are used, then device complexity is reduced, but routing resource requirements increase
Solution Approach 1:
The gate electrode serves multiple functions: it provides the primary gate control for the CFET device and simultaneously houses the isolated conductive structure that enables lateral electrical connections between adjacent circuit elements. This multi-functionality of the gate electrode structure eliminates the need for separate dedicated routing resources for isolated connections, reducing overall routing resource requirements.
Data Source
AI summary
A method of forming an IC device includes creating a recess by removing at least a portion of a channel of a first transistor and a portion of a gate electrode, the gate electrode being common to the first transistor and an underlying second transistor. The method includes filling the recess with a dielectric material to form an isolation layer, and constructing a slot via overlying the isolation layer.