Patterned CFET Gate Edges for Lower Parasitic Capacitance
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Solution Overview
Problem
Parasitic capacitance between gate and source/drain electrodes in semiconductor devices increases hyperbolically with scaling, complicating device performance and etching processes for tall structures.
Innovation Solution
Pattern the gate edges with concave or convex surfaces using multiple etching processes to reduce capacitance, and employ inner and outer spacers to control gate extension and isolate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are scaled down, then overall device performance is improved, but parasitic capacitance between gate and source/drain electrodes increases hyperbolically
Solution Approach 1:
The patent applies curvature by forming concave or convex surfaces on the gate edges instead of maintaining straight vertical profiles. This curvature modifies the electric field distribution and reduces the overlap between gate and source/drain electrodes, thereby reducing parasitic capacitance while maintaining scaled device dimensions for improved performance
2Manufacturing precision
If perfectly straight vertical patterning is used for tall gate structures, then manufacturing precision is improved, but etching process complexity increases
Solution Approach 1:
The patent segments the gate structure into multiple sections (upper section with first edge profile, lower section with second edge profile) and uses multiple etching recipes to create different profiles in different sections. This segmentation allows each etching process to be optimized for its specific section, achieving precise patterning while simplifying the overall process by using standard etching techniques rather than requiring perfectly straight vertical patterning throughout
Data Source
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AI summary
A semiconductor and method for fabrication of the semiconductor device having a patterned gate to reduce the parasitic capacitance in a field effect transistor ("FET"), particularly a complementary field effect transistor ("CFET"). The patterned gate has edges along the longitudinal axis of the gate from top to bottom that are convex or concave. The gate and semiconductors are electrically isolated by inner and outer spacers.