3D CFET Gate Formation via Vertical Etching and Independent Contacts
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Solution Overview
Problem
Conventional 2D semiconductor scaling faces challenges in maintaining node-to-node improvements in power-performance-area-cost (PPAC) as it enters single-digit nanometer fabrication nodes, and existing methods struggle to efficiently implement 3D integration for random logic designs, which is complex and costly.
Innovation Solution
A method for manufacturing 3D semiconductor devices involving the formation of upper and bottom gates with a dielectric separation layer, where material is removed through etching to create diffusion breaks and cuts, allowing independent electrical connections to each gate, enabling a CFET architecture with shared and independent N and P gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D scaling is used to increase transistor density, then transistor density per unit area improves, but manufacturing complexity and cost increase significantly at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from conventional 2D planar transistor architecture to 3D vertically stacked CFET architecture. By stacking n-type and p-type transistors vertically with shared gates, the invention achieves higher transistor density per unit area while simplifying the manufacturing process through simultaneous formation of multiple transistor components in the vertical dimension, thereby reducing manufacturing complexity at advanced nodes
2Quantity of substance
If 3D integration is implemented for random logic designs, then transistor density in volume increases, but fabrication complexity and cost increase
Solution Approach 1:
The patent merges the formation of diffusion breaks, gate cuts, and independent N and P gates into a single integrated fabrication process. By combining multiple previously separate manufacturing steps into one unified process that simultaneously creates all these features, the invention reduces fabrication complexity and cost while achieving high 3D transistor density for random logic designs
3Area of stationary object
If CFET architecture with stacked transistors is used, then area savings are achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent creates a universal fabrication process that simultaneously performs multiple functions: forming diffusion breaks, creating gate cuts, and constructing independent N and P gates in the CFET structure. This multi-functional approach consolidates several manufacturing operations into one process, reducing overall process complexity while maintaining the area savings benefits of CFET architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density by stacking transistors in the vertical axis, achieving area savings and reducing complexity and cost in the fabrication process, while enabling efficient design for SRAM and logic standard cells.
Implementation Method 1
the removing of material includes removing material in the plurality of material removal areas via an etching process
Data Source
AI summary
A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.