CFET Gate Isolation Layer for Vertically Stacked Gate Electrodes
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in effectively isolating gate electrodes of complementary field-effect transistors (CFETs), leading to potential electrical interference and manufacturing complexities.
Innovation Solution
A method is introduced to form a gate isolation layer between the upper and lower gate electrodes of CFETs, involving etching back the lower gate electrode and filling the resulting seams with a dielectric material to create electrical isolation, while using a by-product generated during the etching process to enhance sealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes of CFETs are isolated using conventional methods, then electrical isolation is achieved, but manufacturing complexity increases
Solution Approach 1:
An intermediate gate isolation layer is introduced between the upper and lower gate electrodes to achieve electrical isolation. This mediator layer simplifies the manufacturing process by providing a straightforward isolation mechanism without requiring complex multi-step procedures
Solution Approach 2:
The gate structure is segmented into distinct upper and lower gate electrodes separated by the gate isolation layer. This segmentation allows independent control and simplification of each gate region, reducing overall manufacturing complexity while maintaining effective electrical isolation
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components are integrated into a given area, but electrical interference between gate electrodes increases
Solution Approach 1:
Instead of increasing horizontal separation distance between gates, the solution moves to the vertical dimension by inserting a gate isolation layer between the upper and lower gate electrodes. This dimensional transition enables effective electrical isolation while maintaining high integration density in the planar direction
3Reliability
If conventional isolation methods are used, then electrical isolation is achieved, but manufacturing process simplification is limited
Solution Approach 1:
The gate isolation layer formation is merged with the existing gate electrode fabrication process flow. By integrating the isolation layer creation into the standard manufacturing sequence, the process achieves electrical isolation without requiring separate complex manufacturing steps, thereby simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively isolates the upper and lower gate electrodes, reducing electrical interference and simplifying the manufacturing process, thereby enhancing the performance and integration density of CFETs.
Implementation Method 1
etching back the lower gate electrode
Implementation Method 2
filling the resulting seams with a dielectric material
Data Source
AI summary
A method includes forming a lower semiconductor region, forming an upper semiconductor region overlapping the lower semiconductor region, forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively, forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric, etching back the lower gate electrode, forming a gate isolation layer on the lower gate electrode that has been etched back, and forming an upper gate electrode over the gate isolation layer. The upper gate electrode is on the upper gate dielectric.