CFET Gate Layout for Independent Pick-Up Without Shorting
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Solution Overview
Problem
The challenge in modern semiconductor device processing is the limited space for independent gate pick-up in complementary field-effect transistors (CFETs), particularly in low track height cells with aggressive line pitches, leading to potential shorting issues and reduced performance.
Innovation Solution
A CFET device design with a tri-gate configuration for the top gate electrode, allowing independent gate pick-up via a via contact portion that protrudes outside the top FET device, and a dielectric wall to separate the bottom gate contact via from the top gate electrode, enabling zero gate extension along outward-facing side surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CFET device is designed with independent gate pick-up in low track height cells, then device performance and drive current are improved, but the risk of shorting between top gate electrode and bottom gate contact via increases
Solution Approach 1:
The top gate electrode is designed with gate prongs that extend laterally in the horizontal plane, allowing the via contact portion to protrude outside the top FET device footprint. This dimensional reconfiguration enables independent gate pick-up while maintaining safe vertical separation from the bottom gate contact via, thus improving device performance without increasing shorting risk.
Solution Approach 2:
The top gate electrode is segmented into multiple gate prongs (first gate prongs and second gate prongs) that are spaced apart laterally. This segmentation creates distinct regions for different functions: the gate prongs provide gate control over channel layers, while the via contact portion protruding between them enables independent electrical contact. The segmentation thus resolves the contradiction by separating the gate control function from the contact function in space.
2Area of stationary object
If the top gate electrode is configured with zero gate extension along outward-facing side surfaces, then area efficiency is improved, but access to bottom gate contact via becomes more difficult
Solution Approach 1:
Instead of extending the gate electrode vertically or horizontally beyond the device footprint, the via contact portion is positioned in the lateral dimension between the gate prongs. This allows the gate electrode to maintain zero gate extension along outward-facing side surfaces for area efficiency, while the via contact portion protrudes in the horizontal plane to provide easy access for bottom gate contact via formation.
3Productivity
If aggressive line pitches are used in low track height cells, then routing density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The via contact portion protruding from the top gate electrode serves as an intermediary structure that facilitates precise alignment. By providing a laterally extended contact region between the gate prongs, it creates a larger target area for via formation, thereby reducing the precision requirements for aligning the bottom gate contact via with the bottom gate electrode, even when aggressive line pitches are used to achieve high routing density.
Data Source
AI summary
Example embodiments relate to complementary field-effect transistor (CFET) devices. An example CFET device includes a bottom FET device. The bottom FET device includes a bottom channel nanostructure having a first side surface oriented in a first direction. The bottom FET device also includes a second side surface oriented in a second direction opposite the first direction. Further, the bottom FET device includes a bottom gate electrode configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure. The bottom gate electrode includes a side gate portion arranged along the first side surface of the bottom channel nanostructure. The CFET device also includes a top FET device stacked on the bottom FET device. The top FET device includes channel layers, a gate electrode, and gate prongs. Additionally, the CFET device includes a top gate contact via. Further, the CFET device includes a bottom gate contact via.