CFET Gate Stack Dipole Film for Multi-VT Without Drive-In
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing minimum feature sizes for increased integration density, which leads to issues such as thermal budget and manufacturing cost increases due to the need for dipole drive-in and film removal processes in transistor fabrication.
Innovation Solution
A method of selectively doping dipole dopants into gate stacks of Complementary Field-Effect Transistors (CFETs) without a dipole drive-in process and no dipole film removal, using interfacial layers and high-k gate dielectrics, allowing for reduced thermal budget and manufacturing costs by forming a dipole film between interfacial layers and high-k dielectrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dipole drive-in process is used to control threshold voltage, then threshold voltage control is improved, but thermal budget increases
Solution Approach 1:
The dipole film is formed between the interfacial layer and high-k dielectric layer before the gate electrode deposition, so that the dipole dopants are already in position to provide the desired threshold voltage effect without requiring subsequent high-temperature drive-in processing
Solution Approach 2:
A dipole film comprising dipole dopants is introduced as an intermediary layer between the interfacial layer and high-k dielectric layer, which mediates the threshold voltage control function without requiring thermal drive-in processes
2Manufacturing precision
If dipole film removal process is performed, then manufacturing precision is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The dipole film is designed to remain in the structure and serve its function continuously, eliminating the need for subsequent removal processes. The dipole dopants in the film provide ongoing threshold voltage control without requiring cleanup steps
Solution Approach 2:
The unnecessary dipole film removal step is extracted from the manufacturing process, simplifying the overall fabrication sequence and reducing costs while the dipole film itself remains to perform its electrical function
3Manufacturing precision
If multiple processing steps are used for dipole doping, then threshold voltage control is improved, but device complexity increases
Solution Approach 1:
The formation of the dipole film is merged with the gate stack formation process, occurring between the interfacial layer and high-k dielectric layer deposition, so that threshold voltage control is integrated into the standard fabrication sequence without adding separate complex doping steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal budget and manufacturing costs while maintaining control over threshold voltages by diffusing dipole dopants into gate dielectrics, enhancing the efficiency and cost-effectiveness of transistor fabrication.
Implementation Method 1
diffusing dipole dopants into gate dielectrics
Data Source
AI summary
A method includes forming a transistor, which includes forming a semiconductor nanostructure, forming an interfacial layer encircling the semiconductor region, depositing a dipole film on the interfacial layer, depositing a high-k dielectric layer on the dipole film, and depositing a gate electrode on the high-k dielectric layer. The formation of the transistor may be free from dipole dopant drive-in process and may be free from dipole film removal process.