CFET Top-Tier Gate Stack With Dipole-First Crystallized High-k
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Solution Overview
Problem
Conventional semiconductor device fabrication methods face challenges in optimizing device performance due to high temperature processes that can damage bottom-tier devices in sequential CFET architectures and the limited dielectric constant of amorphous high-k materials.
Innovation Solution
A dipole-first approach is implemented, forming a dipole layer using materials like yttrium oxide or scandium oxide before the high-k gate dielectric layer, followed by a doped high-k gate dielectric layer that achieves a crystalline phase through annealing, reducing the need for high-temperature processing and enhancing dielectric constant values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high temperature processes are used during fabrication, then certain IC components can be formed, but bottom-tier devices may be damaged
Solution Approach 1:
The dipole layer is formed before the high-k gate dielectric layer, allowing the dipole drive-in process to be performed at lower temperatures (below 500°C) before bottom-tier device formation. This preliminary action sequence prevents thermal damage to bottom-tier devices while still achieving the necessary dipole drive-in for threshold voltage control.
Solution Approach 2:
The conventional sequence is inverted: instead of forming the high-k gate dielectric first and then adding the dipole layer, the dipole layer is formed first followed by the high-k gate dielectric. This inversion allows the dipole drive-in process to occur at lower temperatures that do not damage bottom-tier devices.
2Ease of manufacture
If amorphous high-k gate dielectric materials are used, then fabrication is simplified, but the dielectric constant is limited
Solution Approach 1:
The gate dielectric material undergoes a phase change from amorphous to crystalline through a controlled annealing process. This parameter change increases the dielectric constant from typical amorphous values to crystalline values (e.g., cubic phase HfO2 with κ>20), improving device performance while maintaining fabrication feasibility.
Solution Approach 2:
The high-k gate dielectric material transitions from an amorphous phase to a crystalline phase through thermal annealing. This phase transition significantly enhances the dielectric constant, providing better electrical performance and enabling equivalent oxide thickness scaling without increasing physical thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by minimizing damage to bottom-tier devices and increasing the dielectric constant of the gate dielectric layer, leading to better electrical performance and ease of equivalent oxide thickness scaling.
Implementation Method 1
forming a dipole layer using materials like yttrium oxide or scandium oxide before the high-k gate dielectric layer
Implementation Method 2
followed by a doped high-k gate dielectric layer that achieves a crystalline phase through annealing
Data Source
AI summary
A dipole layer is formed over a semiconductor channel region. A doped gate dielectric layer is formed over the dipole layer. The doped gate dielectric layer contains an amorphous material. Via an annealing process, the amorphous material of the doped gate dielectric layer is converted into a material with at least partially crystal phases. After the doped gate dielectric layer is converted into the layer with partially crystal phases, a metal-containing gate electrode is formed over the doped gate dielectric layer.